1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * This file contains the configuration parameters for the dbau1x00 board. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_DBAU1X00 1 16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ 17 18 #ifdef CONFIG_DBAU1000 19 /* Also known as Merlot */ 20 #define CONFIG_SOC_AU1000 1 21 #else 22 #ifdef CONFIG_DBAU1100 23 #define CONFIG_SOC_AU1100 1 24 #else 25 #ifdef CONFIG_DBAU1500 26 #define CONFIG_SOC_AU1500 1 27 #else 28 #ifdef CONFIG_DBAU1550 29 /* Cabernet */ 30 #define CONFIG_SOC_AU1550 1 31 #else 32 #error "No valid board set" 33 #endif 34 #endif 35 #endif 36 #endif 37 38 #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ 39 40 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ 41 42 #define CONFIG_BAUDRATE 115200 43 44 /* valid baudrates */ 45 46 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 47 #undef CONFIG_BOOTARGS 48 49 #define CONFIG_EXTRA_ENV_SETTINGS \ 50 "addmisc=setenv bootargs ${bootargs} " \ 51 "console=ttyS0,${baudrate} " \ 52 "panic=1\0" \ 53 "bootfile=/tftpboot/vmlinux.srec\0" \ 54 "load=tftp 80500000 ${u-boot}\0" \ 55 "" 56 57 #ifdef CONFIG_DBAU1550 58 /* Boot from flash by default, revert to bootp */ 59 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" 60 #else /* CONFIG_DBAU1550 */ 61 #define CONFIG_BOOTCOMMAND "bootp;bootm" 62 #endif /* CONFIG_DBAU1550 */ 63 64 65 /* 66 * BOOTP options 67 */ 68 #define CONFIG_BOOTP_BOOTFILESIZE 69 #define CONFIG_BOOTP_BOOTPATH 70 #define CONFIG_BOOTP_GATEWAY 71 #define CONFIG_BOOTP_HOSTNAME 72 73 74 /* 75 * Command line configuration. 76 */ 77 #include <config_cmd_default.h> 78 79 #undef CONFIG_CMD_BDI 80 #undef CONFIG_CMD_BEDBUG 81 #undef CONFIG_CMD_ELF 82 #undef CONFIG_CMD_SAVEENV 83 #undef CONFIG_CMD_FAT 84 #undef CONFIG_CMD_FPGA 85 #undef CONFIG_CMD_MII 86 #undef CONFIG_CMD_RUN 87 88 89 #ifdef CONFIG_DBAU1550 90 91 #define CONFIG_CMD_FLASH 92 #define CONFIG_CMD_LOADB 93 #define CONFIG_CMD_NET 94 95 #undef CONFIG_CMD_I2C 96 #undef CONFIG_CMD_IDE 97 #undef CONFIG_CMD_NFS 98 #undef CONFIG_CMD_PCMCIA 99 100 #else 101 102 #define CONFIG_CMD_IDE 103 #define CONFIG_CMD_DHCP 104 105 #undef CONFIG_CMD_FLASH 106 #undef CONFIG_CMD_LOADB 107 #undef CONFIG_CMD_LOADS 108 109 #endif 110 111 112 /* 113 * Miscellaneous configurable options 114 */ 115 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 116 117 #define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */ 118 119 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 120 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 121 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ 122 123 #define CONFIG_SYS_MALLOC_LEN 128*1024 124 125 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 126 127 #define CONFIG_SYS_MHZ 396 128 129 #if (CONFIG_SYS_MHZ % 12) != 0 130 #error "Invalid CPU frequency - must be multiple of 12!" 131 #endif 132 133 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 134 135 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ 136 137 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ 138 139 #define CONFIG_SYS_MEMTEST_START 0x80100000 140 #define CONFIG_SYS_MEMTEST_END 0x80800000 141 142 /*----------------------------------------------------------------------- 143 * FLASH and environment organization 144 */ 145 #ifdef CONFIG_DBAU1550 146 147 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 148 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ 149 150 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ 151 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ 152 153 #else /* CONFIG_DBAU1550 */ 154 155 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 156 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ 157 158 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ 159 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ 160 161 #endif /* CONFIG_DBAU1550 */ 162 163 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} 164 165 #define CONFIG_SYS_FLASH_CFI 1 166 #define CONFIG_FLASH_CFI_DRIVER 1 167 168 /* The following #defines are needed to get flash environment right */ 169 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 170 #define CONFIG_SYS_MONITOR_LEN (192 << 10) 171 172 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 173 174 /* We boot from this flash, selected with dip switch */ 175 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 176 177 /* timeout values are in ticks */ 178 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 179 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 180 181 #define CONFIG_ENV_IS_NOWHERE 1 182 183 /* Address and size of Primary Environment Sector */ 184 #define CONFIG_ENV_ADDR 0xB0030000 185 #define CONFIG_ENV_SIZE 0x10000 186 187 #define CONFIG_FLASH_16BIT 188 189 #define CONFIG_NR_DRAM_BANKS 2 190 191 192 #ifdef CONFIG_DBAU1550 193 #define MEM_SIZE 192 194 #else 195 #define MEM_SIZE 64 196 #endif 197 198 #define CONFIG_MEMSIZE_IN_BYTES 199 200 #ifndef CONFIG_DBAU1550 201 /*---ATA PCMCIA ------------------------------------*/ 202 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ 203 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 204 #define CONFIG_PCMCIA_SLOT_A 205 206 #define CONFIG_ATAPI 1 207 #define CONFIG_MAC_PARTITION 1 208 209 /* We run CF in "true ide" mode or a harddrive via pcmcia */ 210 #define CONFIG_IDE_PCMCIA 1 211 212 /* We only support one slot for now */ 213 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 214 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 215 216 #undef CONFIG_IDE_LED /* LED for ide not supported */ 217 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 218 219 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 220 221 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 222 223 /* Offset for data I/O */ 224 #define CONFIG_SYS_ATA_DATA_OFFSET 8 225 226 /* Offset for normal register accesses */ 227 #define CONFIG_SYS_ATA_REG_OFFSET 0 228 229 /* Offset for alternate registers */ 230 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 231 #endif /* CONFIG_DBAU1550 */ 232 233 /*----------------------------------------------------------------------- 234 * Cache Configuration 235 */ 236 #define CONFIG_SYS_DCACHE_SIZE 16384 237 #define CONFIG_SYS_ICACHE_SIZE 16384 238 #define CONFIG_SYS_CACHELINE_SIZE 32 239 240 #endif /* __CONFIG_H */ 241