1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* 25 * This file contains the configuration parameters for the dbau1x00 board. 26 */ 27 28 #ifndef __CONFIG_H 29 #define __CONFIG_H 30 31 #define CONFIG_MIPS32 1 /* MIPS32 CPU core */ 32 #define CONFIG_DBAU1X00 1 33 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ 34 35 #ifdef CONFIG_DBAU1000 36 /* Also known as Merlot */ 37 #define CONFIG_SOC_AU1000 1 38 #else 39 #ifdef CONFIG_DBAU1100 40 #define CONFIG_SOC_AU1100 1 41 #else 42 #ifdef CONFIG_DBAU1500 43 #define CONFIG_SOC_AU1500 1 44 #else 45 #ifdef CONFIG_DBAU1550 46 /* Cabernet */ 47 #define CONFIG_SOC_AU1550 1 48 #else 49 #error "No valid board set" 50 #endif 51 #endif 52 #endif 53 #endif 54 55 #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ 56 57 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ 58 59 #define CONFIG_BAUDRATE 115200 60 61 /* valid baudrates */ 62 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 63 64 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 65 #undef CONFIG_BOOTARGS 66 67 #define CONFIG_EXTRA_ENV_SETTINGS \ 68 "addmisc=setenv bootargs ${bootargs} " \ 69 "console=ttyS0,${baudrate} " \ 70 "panic=1\0" \ 71 "bootfile=/tftpboot/vmlinux.srec\0" \ 72 "load=tftp 80500000 ${u-boot}\0" \ 73 "" 74 75 #ifdef CONFIG_DBAU1550 76 /* Boot from flash by default, revert to bootp */ 77 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" 78 #else /* CONFIG_DBAU1550 */ 79 #define CONFIG_BOOTCOMMAND "bootp;bootm" 80 #endif /* CONFIG_DBAU1550 */ 81 82 83 /* 84 * BOOTP options 85 */ 86 #define CONFIG_BOOTP_BOOTFILESIZE 87 #define CONFIG_BOOTP_BOOTPATH 88 #define CONFIG_BOOTP_GATEWAY 89 #define CONFIG_BOOTP_HOSTNAME 90 91 92 /* 93 * Command line configuration. 94 */ 95 #include <config_cmd_default.h> 96 97 #undef CONFIG_CMD_BDI 98 #undef CONFIG_CMD_BEDBUG 99 #undef CONFIG_CMD_ELF 100 #undef CONFIG_CMD_SAVEENV 101 #undef CONFIG_CMD_FAT 102 #undef CONFIG_CMD_FPGA 103 #undef CONFIG_CMD_MII 104 #undef CONFIG_CMD_RUN 105 106 107 #ifdef CONFIG_DBAU1550 108 109 #define CONFIG_CMD_FLASH 110 #define CONFIG_CMD_LOADB 111 #define CONFIG_CMD_NET 112 113 #undef CONFIG_CMD_I2C 114 #undef CONFIG_CMD_IDE 115 #undef CONFIG_CMD_NFS 116 #undef CONFIG_CMD_PCMCIA 117 118 #else 119 120 #define CONFIG_CMD_IDE 121 #define CONFIG_CMD_DHCP 122 123 #undef CONFIG_CMD_FLASH 124 #undef CONFIG_CMD_LOADB 125 #undef CONFIG_CMD_LOADS 126 127 #endif 128 129 130 /* 131 * Miscellaneous configurable options 132 */ 133 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 134 135 #define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */ 136 137 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 138 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 139 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ 140 141 #define CONFIG_SYS_MALLOC_LEN 128*1024 142 143 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 144 145 #define CONFIG_SYS_MHZ 396 146 147 #if (CONFIG_SYS_MHZ % 12) != 0 148 #error "Invalid CPU frequency - must be multiple of 12!" 149 #endif 150 151 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 152 153 #define CONFIG_SYS_HZ 1000 154 155 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ 156 157 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ 158 159 #define CONFIG_SYS_MEMTEST_START 0x80100000 160 #define CONFIG_SYS_MEMTEST_END 0x80800000 161 162 /*----------------------------------------------------------------------- 163 * FLASH and environment organization 164 */ 165 #ifdef CONFIG_DBAU1550 166 167 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 168 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ 169 170 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ 171 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ 172 173 #else /* CONFIG_DBAU1550 */ 174 175 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 176 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ 177 178 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ 179 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ 180 181 #endif /* CONFIG_DBAU1550 */ 182 183 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} 184 185 #define CONFIG_SYS_FLASH_CFI 1 186 #define CONFIG_FLASH_CFI_DRIVER 1 187 188 /* The following #defines are needed to get flash environment right */ 189 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE 190 #define CONFIG_SYS_MONITOR_LEN (192 << 10) 191 192 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 193 194 /* We boot from this flash, selected with dip switch */ 195 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 196 197 /* timeout values are in ticks */ 198 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 199 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 200 201 #define CONFIG_ENV_IS_NOWHERE 1 202 203 /* Address and size of Primary Environment Sector */ 204 #define CONFIG_ENV_ADDR 0xB0030000 205 #define CONFIG_ENV_SIZE 0x10000 206 207 #define CONFIG_FLASH_16BIT 208 209 #define CONFIG_NR_DRAM_BANKS 2 210 211 #define CONFIG_NET_MULTI 212 213 #ifdef CONFIG_DBAU1550 214 #define MEM_SIZE 192 215 #else 216 #define MEM_SIZE 64 217 #endif 218 219 #define CONFIG_MEMSIZE_IN_BYTES 220 221 #ifndef CONFIG_DBAU1550 222 /*---ATA PCMCIA ------------------------------------*/ 223 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ 224 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 225 #define CONFIG_PCMCIA_SLOT_A 226 227 #define CONFIG_ATAPI 1 228 #define CONFIG_MAC_PARTITION 1 229 230 /* We run CF in "true ide" mode or a harddrive via pcmcia */ 231 #define CONFIG_IDE_PCMCIA 1 232 233 /* We only support one slot for now */ 234 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 235 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 236 237 #undef CONFIG_IDE_LED /* LED for ide not supported */ 238 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 239 240 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 241 242 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 243 244 /* Offset for data I/O */ 245 #define CONFIG_SYS_ATA_DATA_OFFSET 8 246 247 /* Offset for normal register accesses */ 248 #define CONFIG_SYS_ATA_REG_OFFSET 0 249 250 /* Offset for alternate registers */ 251 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 252 #endif /* CONFIG_DBAU1550 */ 253 254 /*----------------------------------------------------------------------- 255 * Cache Configuration 256 */ 257 #define CONFIG_SYS_DCACHE_SIZE 16384 258 #define CONFIG_SYS_ICACHE_SIZE 16384 259 #define CONFIG_SYS_CACHELINE_SIZE 32 260 261 #endif /* __CONFIG_H */ 262