1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * This file contains the configuration parameters for the dbau1x00 board. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_DBAU1X00 1 16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ 17 18 #ifdef CONFIG_DBAU1000 19 /* Also known as Merlot */ 20 #define CONFIG_SOC_AU1000 1 21 #else 22 #ifdef CONFIG_DBAU1100 23 #define CONFIG_SOC_AU1100 1 24 #else 25 #ifdef CONFIG_DBAU1500 26 #define CONFIG_SOC_AU1500 1 27 #else 28 #ifdef CONFIG_DBAU1550 29 /* Cabernet */ 30 #define CONFIG_SOC_AU1550 1 31 #else 32 #error "No valid board set" 33 #endif 34 #endif 35 #endif 36 #endif 37 38 /* valid baudrates */ 39 40 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 41 42 #define CONFIG_EXTRA_ENV_SETTINGS \ 43 "addmisc=setenv bootargs ${bootargs} " \ 44 "console=ttyS0,${baudrate} " \ 45 "panic=1\0" \ 46 "bootfile=/tftpboot/vmlinux.srec\0" \ 47 "load=tftp 80500000 ${u-boot}\0" \ 48 "" 49 50 #ifdef CONFIG_DBAU1550 51 /* Boot from flash by default, revert to bootp */ 52 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" 53 #else /* CONFIG_DBAU1550 */ 54 #define CONFIG_BOOTCOMMAND "bootp;bootm" 55 #endif /* CONFIG_DBAU1550 */ 56 57 /* 58 * BOOTP options 59 */ 60 #define CONFIG_BOOTP_BOOTFILESIZE 61 #define CONFIG_BOOTP_BOOTPATH 62 #define CONFIG_BOOTP_GATEWAY 63 #define CONFIG_BOOTP_HOSTNAME 64 65 /* 66 * Command line configuration. 67 */ 68 69 /* 70 * Miscellaneous configurable options 71 */ 72 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 73 74 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ 75 76 #define CONFIG_SYS_MALLOC_LEN 128*1024 77 78 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 79 80 #define CONFIG_SYS_MHZ 396 81 82 #if (CONFIG_SYS_MHZ % 12) != 0 83 #error "Invalid CPU frequency - must be multiple of 12!" 84 #endif 85 86 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 87 88 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ 89 90 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ 91 92 #define CONFIG_SYS_MEMTEST_START 0x80100000 93 #define CONFIG_SYS_MEMTEST_END 0x80800000 94 95 /*----------------------------------------------------------------------- 96 * FLASH and environment organization 97 */ 98 #ifdef CONFIG_DBAU1550 99 100 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 101 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ 102 103 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ 104 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ 105 106 #else /* CONFIG_DBAU1550 */ 107 108 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 109 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ 110 111 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ 112 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ 113 114 #endif /* CONFIG_DBAU1550 */ 115 116 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} 117 118 #define CONFIG_SYS_FLASH_CFI 1 119 #define CONFIG_FLASH_CFI_DRIVER 1 120 121 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 122 #define CONFIG_SYS_MONITOR_LEN (192 << 10) 123 124 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 125 126 /* We boot from this flash, selected with dip switch */ 127 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 128 129 /* timeout values are in ticks */ 130 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 131 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 132 133 /* Address and size of Primary Environment Sector */ 134 #define CONFIG_ENV_ADDR 0xB0030000 135 #define CONFIG_ENV_SIZE 0x10000 136 137 #define CONFIG_FLASH_16BIT 138 139 #define CONFIG_NR_DRAM_BANKS 2 140 141 #ifdef CONFIG_DBAU1550 142 #define MEM_SIZE 192 143 #else 144 #define MEM_SIZE 64 145 #endif 146 147 #define CONFIG_MEMSIZE_IN_BYTES 148 149 #ifndef CONFIG_DBAU1550 150 /*---ATA PCMCIA ------------------------------------*/ 151 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ 152 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 153 #define CONFIG_PCMCIA_SLOT_A 154 155 #define CONFIG_ATAPI 1 156 157 /* We run CF in "true ide" mode or a harddrive via pcmcia */ 158 #define CONFIG_IDE_PCMCIA 1 159 160 /* We only support one slot for now */ 161 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 162 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 163 164 #undef CONFIG_IDE_LED /* LED for ide not supported */ 165 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 166 167 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 168 169 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 170 171 /* Offset for data I/O */ 172 #define CONFIG_SYS_ATA_DATA_OFFSET 8 173 174 /* Offset for normal register accesses */ 175 #define CONFIG_SYS_ATA_REG_OFFSET 0 176 177 /* Offset for alternate registers */ 178 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 179 #endif /* CONFIG_DBAU1550 */ 180 181 #endif /* __CONFIG_H */ 182