1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * This file contains the configuration parameters for the dbau1x00 board. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_DBAU1X00 1 16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ 17 18 #ifdef CONFIG_DBAU1000 19 /* Also known as Merlot */ 20 #define CONFIG_SOC_AU1000 1 21 #else 22 #ifdef CONFIG_DBAU1100 23 #define CONFIG_SOC_AU1100 1 24 #else 25 #ifdef CONFIG_DBAU1500 26 #define CONFIG_SOC_AU1500 1 27 #else 28 #ifdef CONFIG_DBAU1550 29 /* Cabernet */ 30 #define CONFIG_SOC_AU1550 1 31 #else 32 #error "No valid board set" 33 #endif 34 #endif 35 #endif 36 #endif 37 38 /* valid baudrates */ 39 40 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 41 42 #define CONFIG_EXTRA_ENV_SETTINGS \ 43 "addmisc=setenv bootargs ${bootargs} " \ 44 "console=ttyS0,${baudrate} " \ 45 "panic=1\0" \ 46 "bootfile=/tftpboot/vmlinux.srec\0" \ 47 "load=tftp 80500000 ${u-boot}\0" \ 48 "" 49 50 #ifdef CONFIG_DBAU1550 51 /* Boot from flash by default, revert to bootp */ 52 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" 53 #else /* CONFIG_DBAU1550 */ 54 #define CONFIG_BOOTCOMMAND "bootp;bootm" 55 #endif /* CONFIG_DBAU1550 */ 56 57 /* 58 * BOOTP options 59 */ 60 #define CONFIG_BOOTP_BOOTFILESIZE 61 #define CONFIG_BOOTP_BOOTPATH 62 #define CONFIG_BOOTP_GATEWAY 63 #define CONFIG_BOOTP_HOSTNAME 64 65 /* 66 * Command line configuration. 67 */ 68 69 /* 70 * Miscellaneous configurable options 71 */ 72 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 73 74 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 75 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ 76 77 #define CONFIG_SYS_MALLOC_LEN 128*1024 78 79 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 80 81 #define CONFIG_SYS_MHZ 396 82 83 #if (CONFIG_SYS_MHZ % 12) != 0 84 #error "Invalid CPU frequency - must be multiple of 12!" 85 #endif 86 87 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 88 89 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ 90 91 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ 92 93 #define CONFIG_SYS_MEMTEST_START 0x80100000 94 #define CONFIG_SYS_MEMTEST_END 0x80800000 95 96 /*----------------------------------------------------------------------- 97 * FLASH and environment organization 98 */ 99 #ifdef CONFIG_DBAU1550 100 101 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 102 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ 103 104 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ 105 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ 106 107 #else /* CONFIG_DBAU1550 */ 108 109 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 110 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ 111 112 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ 113 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ 114 115 #endif /* CONFIG_DBAU1550 */ 116 117 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} 118 119 #define CONFIG_SYS_FLASH_CFI 1 120 #define CONFIG_FLASH_CFI_DRIVER 1 121 122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 123 #define CONFIG_SYS_MONITOR_LEN (192 << 10) 124 125 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 126 127 /* We boot from this flash, selected with dip switch */ 128 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 129 130 /* timeout values are in ticks */ 131 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 132 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 133 134 /* Address and size of Primary Environment Sector */ 135 #define CONFIG_ENV_ADDR 0xB0030000 136 #define CONFIG_ENV_SIZE 0x10000 137 138 #define CONFIG_FLASH_16BIT 139 140 #define CONFIG_NR_DRAM_BANKS 2 141 142 #ifdef CONFIG_DBAU1550 143 #define MEM_SIZE 192 144 #else 145 #define MEM_SIZE 64 146 #endif 147 148 #define CONFIG_MEMSIZE_IN_BYTES 149 150 #ifndef CONFIG_DBAU1550 151 /*---ATA PCMCIA ------------------------------------*/ 152 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ 153 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 154 #define CONFIG_PCMCIA_SLOT_A 155 156 #define CONFIG_ATAPI 1 157 158 /* We run CF in "true ide" mode or a harddrive via pcmcia */ 159 #define CONFIG_IDE_PCMCIA 1 160 161 /* We only support one slot for now */ 162 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 163 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 164 165 #undef CONFIG_IDE_LED /* LED for ide not supported */ 166 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 167 168 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 169 170 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 171 172 /* Offset for data I/O */ 173 #define CONFIG_SYS_ATA_DATA_OFFSET 8 174 175 /* Offset for normal register accesses */ 176 #define CONFIG_SYS_ATA_REG_OFFSET 0 177 178 /* Offset for alternate registers */ 179 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 180 #endif /* CONFIG_DBAU1550 */ 181 182 #endif /* __CONFIG_H */ 183