1 /* 2 * (C) Copyright 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* 9 * This file contains the configuration parameters for the dbau1x00 board. 10 */ 11 12 #ifndef __CONFIG_H 13 #define __CONFIG_H 14 15 #define CONFIG_DBAU1X00 1 16 #define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */ 17 18 #define CONFIG_DISPLAY_BOARDINFO 19 20 #ifdef CONFIG_DBAU1000 21 /* Also known as Merlot */ 22 #define CONFIG_SOC_AU1000 1 23 #else 24 #ifdef CONFIG_DBAU1100 25 #define CONFIG_SOC_AU1100 1 26 #else 27 #ifdef CONFIG_DBAU1500 28 #define CONFIG_SOC_AU1500 1 29 #else 30 #ifdef CONFIG_DBAU1550 31 /* Cabernet */ 32 #define CONFIG_SOC_AU1550 1 33 #else 34 #error "No valid board set" 35 #endif 36 #endif 37 #endif 38 #endif 39 40 #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ 41 42 #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ 43 44 #define CONFIG_BAUDRATE 115200 45 46 /* valid baudrates */ 47 48 #define CONFIG_TIMESTAMP /* Print image info with timestamp */ 49 #undef CONFIG_BOOTARGS 50 51 #define CONFIG_EXTRA_ENV_SETTINGS \ 52 "addmisc=setenv bootargs ${bootargs} " \ 53 "console=ttyS0,${baudrate} " \ 54 "panic=1\0" \ 55 "bootfile=/tftpboot/vmlinux.srec\0" \ 56 "load=tftp 80500000 ${u-boot}\0" \ 57 "" 58 59 #ifdef CONFIG_DBAU1550 60 /* Boot from flash by default, revert to bootp */ 61 #define CONFIG_BOOTCOMMAND "bootm 0xbfc20000; bootp; bootm" 62 #else /* CONFIG_DBAU1550 */ 63 #define CONFIG_BOOTCOMMAND "bootp;bootm" 64 #endif /* CONFIG_DBAU1550 */ 65 66 67 /* 68 * BOOTP options 69 */ 70 #define CONFIG_BOOTP_BOOTFILESIZE 71 #define CONFIG_BOOTP_BOOTPATH 72 #define CONFIG_BOOTP_GATEWAY 73 #define CONFIG_BOOTP_HOSTNAME 74 75 76 /* 77 * Command line configuration. 78 */ 79 #include <config_cmd_default.h> 80 81 #undef CONFIG_CMD_BDI 82 #undef CONFIG_CMD_BEDBUG 83 #undef CONFIG_CMD_ELF 84 #undef CONFIG_CMD_SAVEENV 85 #undef CONFIG_CMD_FAT 86 #undef CONFIG_CMD_FPGA 87 #undef CONFIG_CMD_MII 88 #undef CONFIG_CMD_RUN 89 90 91 #ifdef CONFIG_DBAU1550 92 93 #define CONFIG_CMD_FLASH 94 #define CONFIG_CMD_LOADB 95 #define CONFIG_CMD_NET 96 97 #undef CONFIG_CMD_I2C 98 #undef CONFIG_CMD_IDE 99 #undef CONFIG_CMD_NFS 100 #undef CONFIG_CMD_PCMCIA 101 102 #else 103 104 #define CONFIG_CMD_IDE 105 #define CONFIG_CMD_DHCP 106 107 #undef CONFIG_CMD_FLASH 108 #undef CONFIG_CMD_LOADB 109 #undef CONFIG_CMD_LOADS 110 111 #endif 112 113 114 /* 115 * Miscellaneous configurable options 116 */ 117 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 118 119 #define CONFIG_SYS_PROMPT "DbAu1xx0 # " /* Monitor Command Prompt */ 120 121 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 122 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 123 #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ 124 125 #define CONFIG_SYS_MALLOC_LEN 128*1024 126 127 #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 128 129 #define CONFIG_SYS_MHZ 396 130 131 #if (CONFIG_SYS_MHZ % 12) != 0 132 #error "Invalid CPU frequency - must be multiple of 12!" 133 #endif 134 135 #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000) 136 137 #define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */ 138 139 #define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */ 140 141 #define CONFIG_SYS_MEMTEST_START 0x80100000 142 #define CONFIG_SYS_MEMTEST_END 0x80800000 143 144 /*----------------------------------------------------------------------- 145 * FLASH and environment organization 146 */ 147 #ifdef CONFIG_DBAU1550 148 149 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 150 #define CONFIG_SYS_MAX_FLASH_SECT (512) /* max number of sectors on one chip */ 151 152 #define PHYS_FLASH_1 0xb8000000 /* Flash Bank #1 */ 153 #define PHYS_FLASH_2 0xbc000000 /* Flash Bank #2 */ 154 155 #else /* CONFIG_DBAU1550 */ 156 157 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 158 #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ 159 160 #define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */ 161 #define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */ 162 163 #endif /* CONFIG_DBAU1550 */ 164 165 #define CONFIG_SYS_FLASH_BANKS_LIST {PHYS_FLASH_1, PHYS_FLASH_2} 166 167 #define CONFIG_SYS_FLASH_CFI 1 168 #define CONFIG_FLASH_CFI_DRIVER 1 169 170 /* The following #defines are needed to get flash environment right */ 171 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 172 #define CONFIG_SYS_MONITOR_LEN (192 << 10) 173 174 #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 175 176 /* We boot from this flash, selected with dip switch */ 177 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_2 178 179 /* timeout values are in ticks */ 180 #define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 181 #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ 182 183 #define CONFIG_ENV_IS_NOWHERE 1 184 185 /* Address and size of Primary Environment Sector */ 186 #define CONFIG_ENV_ADDR 0xB0030000 187 #define CONFIG_ENV_SIZE 0x10000 188 189 #define CONFIG_FLASH_16BIT 190 191 #define CONFIG_NR_DRAM_BANKS 2 192 193 194 #ifdef CONFIG_DBAU1550 195 #define MEM_SIZE 192 196 #else 197 #define MEM_SIZE 64 198 #endif 199 200 #define CONFIG_MEMSIZE_IN_BYTES 201 202 #ifndef CONFIG_DBAU1550 203 /*---ATA PCMCIA ------------------------------------*/ 204 #define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */ 205 #define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000 206 #define CONFIG_PCMCIA_SLOT_A 207 208 #define CONFIG_ATAPI 1 209 #define CONFIG_MAC_PARTITION 1 210 211 /* We run CF in "true ide" mode or a harddrive via pcmcia */ 212 #define CONFIG_IDE_PCMCIA 1 213 214 /* We only support one slot for now */ 215 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 216 #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 217 218 #undef CONFIG_IDE_LED /* LED for ide not supported */ 219 #undef CONFIG_IDE_RESET /* reset for ide not supported */ 220 221 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 222 223 #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 224 225 /* Offset for data I/O */ 226 #define CONFIG_SYS_ATA_DATA_OFFSET 8 227 228 /* Offset for normal register accesses */ 229 #define CONFIG_SYS_ATA_REG_OFFSET 0 230 231 /* Offset for alternate registers */ 232 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 233 #endif /* CONFIG_DBAU1550 */ 234 235 /*----------------------------------------------------------------------- 236 * Cache Configuration 237 */ 238 #define CONFIG_SYS_DCACHE_SIZE 16384 239 #define CONFIG_SYS_ICACHE_SIZE 16384 240 #define CONFIG_SYS_CACHELINE_SIZE 32 241 242 #endif /* __CONFIG_H */ 243