1 /* 2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_MV7846MP_GP_H 8 #define _CONFIG_DB_MV7846MP_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_ARMADA_XP /* SOC Family Name */ 14 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 15 16 #define CONFIG_DISPLAY_BOARDINFO_LATE 17 18 /* 19 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 20 * for DDR ECC byte filling in the SPL before loading the main 21 * U-Boot into it. 22 */ 23 #define CONFIG_SYS_TEXT_BASE 0x00800000 24 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 25 26 /* 27 * Commands configuration 28 */ 29 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 30 #define CONFIG_CMD_DHCP 31 #define CONFIG_CMD_ENV 32 #define CONFIG_CMD_I2C 33 #define CONFIG_CMD_NAND 34 #define CONFIG_CMD_PCI 35 #define CONFIG_CMD_PING 36 #define CONFIG_CMD_SATA 37 #define CONFIG_CMD_SF 38 #define CONFIG_CMD_SPI 39 #define CONFIG_CMD_TFTPPUT 40 #define CONFIG_CMD_TIME 41 42 /* I2C */ 43 #define CONFIG_SYS_I2C 44 #define CONFIG_SYS_I2C_MVTWSI 45 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 46 #define CONFIG_SYS_I2C_SLAVE 0x0 47 #define CONFIG_SYS_I2C_SPEED 100000 48 49 /* USB/EHCI configuration */ 50 #define CONFIG_EHCI_IS_TDI 51 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 52 53 /* SPI NOR flash default params, used by sf commands */ 54 #define CONFIG_SF_DEFAULT_SPEED 1000000 55 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 56 57 /* Environment in SPI NOR flash */ 58 #define CONFIG_ENV_IS_IN_SPI_FLASH 59 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 60 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 61 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 62 63 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 64 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 65 66 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 67 #define CONFIG_SYS_ALT_MEMTEST 68 69 /* SATA support */ 70 #define CONFIG_SYS_SATA_MAX_DEVICE 2 71 #define CONFIG_SATA_MV 72 #define CONFIG_LIBATA 73 #define CONFIG_LBA48 74 #define CONFIG_EFI_PARTITION 75 #define CONFIG_DOS_PARTITION 76 77 /* PCIe support */ 78 #ifndef CONFIG_SPL_BUILD 79 #define CONFIG_PCI 80 #define CONFIG_PCI_MVEBU 81 #define CONFIG_PCI_PNP 82 #define CONFIG_PCI_SCAN_SHOW 83 #endif 84 85 /* NAND */ 86 #define CONFIG_SYS_NAND_USE_FLASH_BBT 87 #define CONFIG_SYS_NAND_ONFI_DETECTION 88 89 /* 90 * mv-common.h should be defined after CMD configs since it used them 91 * to enable certain macros 92 */ 93 #include "mv-common.h" 94 95 /* 96 * Memory layout while starting into the bin_hdr via the 97 * BootROM: 98 * 99 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 100 * 0x4000.4030 bin_hdr start address 101 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 102 * 0x4007.fffc BootROM stack top 103 * 104 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 105 * L2 cache thus cannot be used. 106 */ 107 108 /* SPL */ 109 /* Defines for SPL */ 110 #define CONFIG_SPL_FRAMEWORK 111 #define CONFIG_SPL_TEXT_BASE 0x40004030 112 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 113 114 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 115 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 116 117 #ifdef CONFIG_SPL_BUILD 118 #define CONFIG_SYS_MALLOC_SIMPLE 119 #endif 120 121 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 122 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 123 124 #define CONFIG_SPL_LIBCOMMON_SUPPORT 125 #define CONFIG_SPL_LIBGENERIC_SUPPORT 126 #define CONFIG_SPL_SERIAL_SUPPORT 127 #define CONFIG_SPL_I2C_SUPPORT 128 129 /* SPL related SPI defines */ 130 #define CONFIG_SPL_SPI_SUPPORT 131 #define CONFIG_SPL_SPI_FLASH_SUPPORT 132 #define CONFIG_SPL_SPI_LOAD 133 #define CONFIG_SPL_SPI_BUS 0 134 #define CONFIG_SPL_SPI_CS 0 135 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 136 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 137 138 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 139 #define CONFIG_SYS_MVEBU_DDR_AXP 140 #define CONFIG_SPD_EEPROM 0x4e 141 142 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 143