1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_MV7846MP_GP_H 8 #define _CONFIG_DB_MV7846MP_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_ARMADA_XP /* SOC Family Name */ 14 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 15 16 #define CONFIG_DISPLAY_BOARDINFO_LATE 17 18 /* 19 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 20 * for DDR ECC byte filling in the SPL before loading the main 21 * U-Boot into it. 22 */ 23 #define CONFIG_SYS_TEXT_BASE 0x00800000 24 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 25 26 /* 27 * Commands configuration 28 */ 29 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 30 #define CONFIG_CMD_DHCP 31 #define CONFIG_CMD_ENV 32 #define CONFIG_CMD_I2C 33 #define CONFIG_CMD_IDE 34 #define CONFIG_CMD_NAND 35 #define CONFIG_CMD_PCI 36 #define CONFIG_CMD_PING 37 #define CONFIG_CMD_SF 38 #define CONFIG_CMD_SPI 39 #define CONFIG_CMD_TFTPPUT 40 #define CONFIG_CMD_TIME 41 42 /* I2C */ 43 #define CONFIG_SYS_I2C 44 #define CONFIG_SYS_I2C_MVTWSI 45 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 46 #define CONFIG_SYS_I2C_SLAVE 0x0 47 #define CONFIG_SYS_I2C_SPEED 100000 48 49 /* USB/EHCI configuration */ 50 #define CONFIG_EHCI_IS_TDI 51 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 52 53 /* SPI NOR flash default params, used by sf commands */ 54 #define CONFIG_SF_DEFAULT_SPEED 1000000 55 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 56 57 /* Environment in SPI NOR flash */ 58 #define CONFIG_ENV_IS_IN_SPI_FLASH 59 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 60 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 61 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 62 63 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 64 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 65 66 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 67 #define CONFIG_SYS_ALT_MEMTEST 68 69 /* SATA support */ 70 #ifdef CONFIG_CMD_IDE 71 #define __io 72 #define CONFIG_IDE_PREINIT 73 #define CONFIG_MVSATA_IDE 74 75 /* Needs byte-swapping for ATA data register */ 76 #define CONFIG_IDE_SWAP_IO 77 78 #define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */ 79 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */ 80 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 81 82 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 83 #define CONFIG_SYS_ATA_STRIDE 4 84 85 /* CONFIG_CMD_IDE requires some #defines for ATA registers */ 86 #define CONFIG_SYS_IDE_MAXBUS 2 87 #define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS 88 89 /* ATA registers base is at SATA controller base */ 90 #define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE 91 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000 92 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000 93 94 #define CONFIG_DOS_PARTITION 95 #endif /* CONFIG_CMD_IDE */ 96 97 /* PCIe support */ 98 #ifndef CONFIG_SPL_BUILD 99 #define CONFIG_PCI 100 #define CONFIG_PCI_MVEBU 101 #define CONFIG_PCI_PNP 102 #define CONFIG_PCI_SCAN_SHOW 103 #endif 104 105 /* NAND */ 106 #define CONFIG_SYS_NAND_USE_FLASH_BBT 107 #define CONFIG_SYS_NAND_ONFI_DETECTION 108 109 /* 110 * mv-common.h should be defined after CMD configs since it used them 111 * to enable certain macros 112 */ 113 #include "mv-common.h" 114 115 /* 116 * Memory layout while starting into the bin_hdr via the 117 * BootROM: 118 * 119 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 120 * 0x4000.4030 bin_hdr start address 121 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 122 * 0x4007.fffc BootROM stack top 123 * 124 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 125 * L2 cache thus cannot be used. 126 */ 127 128 /* SPL */ 129 /* Defines for SPL */ 130 #define CONFIG_SPL_FRAMEWORK 131 #define CONFIG_SPL_TEXT_BASE 0x40004030 132 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 133 134 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 135 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 136 137 #ifdef CONFIG_SPL_BUILD 138 #define CONFIG_SYS_MALLOC_SIMPLE 139 #endif 140 141 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 142 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 143 144 #define CONFIG_SPL_LIBCOMMON_SUPPORT 145 #define CONFIG_SPL_LIBGENERIC_SUPPORT 146 #define CONFIG_SPL_SERIAL_SUPPORT 147 #define CONFIG_SPL_I2C_SUPPORT 148 149 /* SPL related SPI defines */ 150 #define CONFIG_SPL_SPI_SUPPORT 151 #define CONFIG_SPL_SPI_FLASH_SUPPORT 152 #define CONFIG_SPL_SPI_LOAD 153 #define CONFIG_SPL_SPI_BUS 0 154 #define CONFIG_SPL_SPI_CS 0 155 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 156 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 157 158 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 159 #define CONFIG_SYS_MVEBU_DDR_AXP 160 #define CONFIG_SPD_EEPROM 0x4e 161 162 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 163