1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_MV7846MP_GP_H 8 #define _CONFIG_DB_MV7846MP_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_ARMADA_XP /* SOC Family Name */ 14 #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 15 16 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 17 #define CONFIG_SYS_GENERIC_BOARD 18 #define CONFIG_DISPLAY_BOARDINFO_LATE 19 20 #define CONFIG_SYS_TEXT_BASE 0x04000000 21 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22 23 /* 24 * Commands configuration 25 */ 26 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 27 #define CONFIG_CMD_DHCP 28 #define CONFIG_CMD_ENV 29 #define CONFIG_CMD_I2C 30 #define CONFIG_CMD_IDE 31 #define CONFIG_CMD_PING 32 #define CONFIG_CMD_SF 33 #define CONFIG_CMD_SPI 34 #define CONFIG_CMD_TFTPPUT 35 #define CONFIG_CMD_TIME 36 #define CONFIG_CMD_USB 37 38 /* I2C */ 39 #define CONFIG_SYS_I2C 40 #define CONFIG_SYS_I2C_MVTWSI 41 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 42 #define CONFIG_SYS_I2C_SLAVE 0x0 43 #define CONFIG_SYS_I2C_SPEED 100000 44 45 /* USB/EHCI configuration */ 46 #define CONFIG_USB_EHCI 47 #define CONFIG_USB_STORAGE 48 #define CONFIG_USB_EHCI_MARVELL 49 #define CONFIG_EHCI_IS_TDI 50 51 /* SPI NOR flash default params, used by sf commands */ 52 #define CONFIG_SF_DEFAULT_SPEED 1000000 53 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 54 #define CONFIG_SPI_FLASH_STMICRO 55 56 /* Environment in SPI NOR flash */ 57 #define CONFIG_ENV_IS_IN_SPI_FLASH 58 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 59 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 60 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 61 62 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 63 #define CONFIG_PHY_ADDR { 0x10, 0x11, 0x12, 0x13 } 64 #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII 65 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 66 #define CONFIG_RESET_PHY_R 67 68 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 69 #define CONFIG_SYS_ALT_MEMTEST 70 71 /* SATA support */ 72 #ifdef CONFIG_CMD_IDE 73 #define __io 74 #define CONFIG_IDE_PREINIT 75 #define CONFIG_MVSATA_IDE 76 77 /* Needs byte-swapping for ATA data register */ 78 #define CONFIG_IDE_SWAP_IO 79 80 #define CONFIG_SYS_ATA_REG_OFFSET 0x0100 /* Offset for register access */ 81 #define CONFIG_SYS_ATA_DATA_OFFSET 0x0100 /* Offset for data I/O */ 82 #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 83 84 /* Each 8-bit ATA register is aligned to a 4-bytes address */ 85 #define CONFIG_SYS_ATA_STRIDE 4 86 87 /* CONFIG_CMD_IDE requires some #defines for ATA registers */ 88 #define CONFIG_SYS_IDE_MAXBUS 2 89 #define CONFIG_SYS_IDE_MAXDEVICE CONFIG_SYS_IDE_MAXBUS 90 91 /* ATA registers base is at SATA controller base */ 92 #define CONFIG_SYS_ATA_BASE_ADDR MVEBU_AXP_SATA_BASE 93 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x2000 94 #define CONFIG_SYS_ATA_IDE1_OFFSET 0x4000 95 96 #define CONFIG_DOS_PARTITION 97 #endif /* CONFIG_CMD_IDE */ 98 99 /* 100 * mv-common.h should be defined after CMD configs since it used them 101 * to enable certain macros 102 */ 103 #include "mv-common.h" 104 105 /* 106 * Memory layout while starting into the bin_hdr via the 107 * BootROM: 108 * 109 * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 110 * 0x4000.4030 bin_hdr start address 111 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 112 * 0x4007.fffc BootROM stack top 113 * 114 * The address space between 0x4007.fffc and 0x400f.fff is not locked in 115 * L2 cache thus cannot be used. 116 */ 117 118 /* SPL */ 119 /* Defines for SPL */ 120 #define CONFIG_SPL_FRAMEWORK 121 #define CONFIG_SPL_TEXT_BASE 0x40004030 122 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 123 124 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 125 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 126 127 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 128 CONFIG_SPL_BSS_MAX_SIZE) 129 #define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) 130 131 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 132 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 133 134 #define CONFIG_SPL_LIBCOMMON_SUPPORT 135 #define CONFIG_SPL_LIBGENERIC_SUPPORT 136 #define CONFIG_SPL_SERIAL_SUPPORT 137 #define CONFIG_SPL_I2C_SUPPORT 138 139 /* SPL related SPI defines */ 140 #define CONFIG_SPL_SPI_SUPPORT 141 #define CONFIG_SPL_SPI_FLASH_SUPPORT 142 #define CONFIG_SPL_SPI_LOAD 143 #define CONFIG_SPL_SPI_BUS 0 144 #define CONFIG_SPL_SPI_CS 0 145 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 146 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 147 148 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 149 #define CONFIG_SYS_MVEBU_DDR_AXP 150 #define CONFIG_SPD_EEPROM 0x4e 151 152 #endif /* _CONFIG_DB_MV7846MP_GP_H */ 153