1dd580801SStefan Roese /* 2dd580801SStefan Roese * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3dd580801SStefan Roese * 4dd580801SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5dd580801SStefan Roese */ 6dd580801SStefan Roese 7dd580801SStefan Roese #ifndef _CONFIG_DB_MV7846MP_GP_H 8dd580801SStefan Roese #define _CONFIG_DB_MV7846MP_GP_H 9dd580801SStefan Roese 10dd580801SStefan Roese /* 11dd580801SStefan Roese * High Level Configuration Options (easy to change) 12dd580801SStefan Roese */ 13dd580801SStefan Roese #define CONFIG_ARMADA_XP /* SOC Family Name */ 142554167cSStefan Roese #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 152554167cSStefan Roese 16dd580801SStefan Roese #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 17dd580801SStefan Roese #define CONFIG_SYS_GENERIC_BOARD 18dd580801SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 19dd580801SStefan Roese 20dd580801SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x04000000 21dd580801SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 22dd580801SStefan Roese 23dd580801SStefan Roese /* 24dd580801SStefan Roese * Commands configuration 25dd580801SStefan Roese */ 26dd580801SStefan Roese #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 27dd580801SStefan Roese #include <config_cmd_default.h> 28dd580801SStefan Roese #define CONFIG_CMD_DHCP 29dd580801SStefan Roese #define CONFIG_CMD_ENV 30dd580801SStefan Roese #define CONFIG_CMD_I2C 31dd580801SStefan Roese #define CONFIG_CMD_PING 32dd580801SStefan Roese #define CONFIG_CMD_SF 33dd580801SStefan Roese #define CONFIG_CMD_SPI 34dd580801SStefan Roese #define CONFIG_CMD_TFTPPUT 35dd580801SStefan Roese #define CONFIG_CMD_TIME 36dd580801SStefan Roese 37dd580801SStefan Roese /* I2C */ 38dd580801SStefan Roese #define CONFIG_SYS_I2C 39dd580801SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 40*dd82242bSPaul Kocialkowski #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 41dd580801SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 42dd580801SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 43dd580801SStefan Roese 44dd580801SStefan Roese /* SPI NOR flash default params, used by sf commands */ 45dd580801SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 46dd580801SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 47dd580801SStefan Roese #define CONFIG_SPI_FLASH_STMICRO 48dd580801SStefan Roese 49dd580801SStefan Roese /* Environment in SPI NOR flash */ 50dd580801SStefan Roese #define CONFIG_ENV_IS_IN_SPI_FLASH 51dd580801SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 52dd580801SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 53dd580801SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 54dd580801SStefan Roese 55dd580801SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 56dd580801SStefan Roese #define CONFIG_PHY_BASE_ADDR 0x10 57dd580801SStefan Roese #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_QSGMII 58dd580801SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 59dd580801SStefan Roese #define CONFIG_RESET_PHY_R 60dd580801SStefan Roese 61dd580801SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 62dd580801SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 63dd580801SStefan Roese 64dd580801SStefan Roese /* 65dd580801SStefan Roese * mv-common.h should be defined after CMD configs since it used them 66dd580801SStefan Roese * to enable certain macros 67dd580801SStefan Roese */ 68dd580801SStefan Roese #include "mv-common.h" 69dd580801SStefan Roese 702554167cSStefan Roese /* 712554167cSStefan Roese * Memory layout while starting into the bin_hdr via the 722554167cSStefan Roese * BootROM: 732554167cSStefan Roese * 742554167cSStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 752554167cSStefan Roese * 0x4000.4030 bin_hdr start address 762554167cSStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 772554167cSStefan Roese * 0x4007.fffc BootROM stack top 782554167cSStefan Roese * 792554167cSStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 802554167cSStefan Roese * L2 cache thus cannot be used. 812554167cSStefan Roese */ 822554167cSStefan Roese 832554167cSStefan Roese /* SPL */ 842554167cSStefan Roese /* Defines for SPL */ 852554167cSStefan Roese #define CONFIG_SPL_FRAMEWORK 862554167cSStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 872554167cSStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 882554167cSStefan Roese 892554167cSStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 902554167cSStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 912554167cSStefan Roese 922554167cSStefan Roese #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 932554167cSStefan Roese CONFIG_SPL_BSS_MAX_SIZE) 942554167cSStefan Roese #define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) 952554167cSStefan Roese 962554167cSStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 972554167cSStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 982554167cSStefan Roese 992554167cSStefan Roese #define CONFIG_SPL_LIBCOMMON_SUPPORT 1002554167cSStefan Roese #define CONFIG_SPL_LIBGENERIC_SUPPORT 1012554167cSStefan Roese #define CONFIG_SPL_SERIAL_SUPPORT 1022554167cSStefan Roese #define CONFIG_SPL_I2C_SUPPORT 1032554167cSStefan Roese #define CONFIG_SPL_LDSCRIPT "arch/arm/mvebu-common/u-boot-spl.lds" 1042554167cSStefan Roese 1052554167cSStefan Roese /* SPL related SPI defines */ 1062554167cSStefan Roese #define CONFIG_SPL_SPI_SUPPORT 1072554167cSStefan Roese #define CONFIG_SPL_SPI_FLASH_SUPPORT 1082554167cSStefan Roese #define CONFIG_SPL_SPI_LOAD 1092554167cSStefan Roese #define CONFIG_SPL_SPI_BUS 0 1102554167cSStefan Roese #define CONFIG_SPL_SPI_CS 0 1112554167cSStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 1122554167cSStefan Roese 1132554167cSStefan Roese /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 1142554167cSStefan Roese #define CONFIG_SYS_MVEBU_DDR 1152554167cSStefan Roese #define CONFIG_SPD_EEPROM 0x4e 1162554167cSStefan Roese 117dd580801SStefan Roese #endif /* _CONFIG_DB_MV7846MP_GP_H */ 118