1dd580801SStefan Roese /* 2*c4be10b5SStefan Roese * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3dd580801SStefan Roese * 4dd580801SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5dd580801SStefan Roese */ 6dd580801SStefan Roese 7dd580801SStefan Roese #ifndef _CONFIG_DB_MV7846MP_GP_H 8dd580801SStefan Roese #define _CONFIG_DB_MV7846MP_GP_H 9dd580801SStefan Roese 10dd580801SStefan Roese /* 11dd580801SStefan Roese * High Level Configuration Options (easy to change) 12dd580801SStefan Roese */ 13dd580801SStefan Roese #define CONFIG_ARMADA_XP /* SOC Family Name */ 142554167cSStefan Roese #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 152554167cSStefan Roese 16dd580801SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 17dd580801SStefan Roese 182923c2d2SStefan Roese /* 192923c2d2SStefan Roese * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 202923c2d2SStefan Roese * for DDR ECC byte filling in the SPL before loading the main 212923c2d2SStefan Roese * U-Boot into it. 222923c2d2SStefan Roese */ 232923c2d2SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00800000 24dd580801SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 25dd580801SStefan Roese 26dd580801SStefan Roese /* 27dd580801SStefan Roese * Commands configuration 28dd580801SStefan Roese */ 29dd580801SStefan Roese #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 30dd580801SStefan Roese #define CONFIG_CMD_DHCP 31dd580801SStefan Roese #define CONFIG_CMD_ENV 32dd580801SStefan Roese #define CONFIG_CMD_I2C 33d6b6303dSStefan Roese #define CONFIG_CMD_NAND 3441e705acSStefan Roese #define CONFIG_CMD_PCI 35dd580801SStefan Roese #define CONFIG_CMD_PING 36*c4be10b5SStefan Roese #define CONFIG_CMD_SATA 37dd580801SStefan Roese #define CONFIG_CMD_SF 38dd580801SStefan Roese #define CONFIG_CMD_SPI 39dd580801SStefan Roese #define CONFIG_CMD_TFTPPUT 40dd580801SStefan Roese #define CONFIG_CMD_TIME 41dd580801SStefan Roese 42dd580801SStefan Roese /* I2C */ 43dd580801SStefan Roese #define CONFIG_SYS_I2C 44dd580801SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 45dd82242bSPaul Kocialkowski #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 46dd580801SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 47dd580801SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 48dd580801SStefan Roese 4949114c87SStefan Roese /* USB/EHCI configuration */ 5049114c87SStefan Roese #define CONFIG_EHCI_IS_TDI 518a333716SAnton Schubert #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 5249114c87SStefan Roese 53dd580801SStefan Roese /* SPI NOR flash default params, used by sf commands */ 54dd580801SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 55dd580801SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 56dd580801SStefan Roese 57dd580801SStefan Roese /* Environment in SPI NOR flash */ 58dd580801SStefan Roese #define CONFIG_ENV_IS_IN_SPI_FLASH 59dd580801SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 60dd580801SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 61dd580801SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 62dd580801SStefan Roese 63dd580801SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 64dd580801SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 65dd580801SStefan Roese 66dd580801SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 67dd580801SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 68dd580801SStefan Roese 69e863f7f0SAnton Schubert /* SATA support */ 70*c4be10b5SStefan Roese #define CONFIG_SYS_SATA_MAX_DEVICE 2 71*c4be10b5SStefan Roese #define CONFIG_SATA_MV 72*c4be10b5SStefan Roese #define CONFIG_LIBATA 73*c4be10b5SStefan Roese #define CONFIG_LBA48 74*c4be10b5SStefan Roese #define CONFIG_EFI_PARTITION 75e863f7f0SAnton Schubert #define CONFIG_DOS_PARTITION 76e863f7f0SAnton Schubert 7741e705acSStefan Roese /* PCIe support */ 786451223aSStefan Roese #ifndef CONFIG_SPL_BUILD 7941e705acSStefan Roese #define CONFIG_PCI 8041e705acSStefan Roese #define CONFIG_PCI_MVEBU 8141e705acSStefan Roese #define CONFIG_PCI_PNP 8241e705acSStefan Roese #define CONFIG_PCI_SCAN_SHOW 836451223aSStefan Roese #endif 8441e705acSStefan Roese 85d6b6303dSStefan Roese /* NAND */ 86d6b6303dSStefan Roese #define CONFIG_SYS_NAND_USE_FLASH_BBT 87d6b6303dSStefan Roese #define CONFIG_SYS_NAND_ONFI_DETECTION 88d6b6303dSStefan Roese 89dd580801SStefan Roese /* 90dd580801SStefan Roese * mv-common.h should be defined after CMD configs since it used them 91dd580801SStefan Roese * to enable certain macros 92dd580801SStefan Roese */ 93dd580801SStefan Roese #include "mv-common.h" 94dd580801SStefan Roese 952554167cSStefan Roese /* 962554167cSStefan Roese * Memory layout while starting into the bin_hdr via the 972554167cSStefan Roese * BootROM: 982554167cSStefan Roese * 992554167cSStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 1002554167cSStefan Roese * 0x4000.4030 bin_hdr start address 1012554167cSStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 1022554167cSStefan Roese * 0x4007.fffc BootROM stack top 1032554167cSStefan Roese * 1042554167cSStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 1052554167cSStefan Roese * L2 cache thus cannot be used. 1062554167cSStefan Roese */ 1072554167cSStefan Roese 1082554167cSStefan Roese /* SPL */ 1092554167cSStefan Roese /* Defines for SPL */ 1102554167cSStefan Roese #define CONFIG_SPL_FRAMEWORK 1112554167cSStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 1122554167cSStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 1132554167cSStefan Roese 1142554167cSStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 1152554167cSStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 1162554167cSStefan Roese 1176451223aSStefan Roese #ifdef CONFIG_SPL_BUILD 1186451223aSStefan Roese #define CONFIG_SYS_MALLOC_SIMPLE 1196451223aSStefan Roese #endif 1202554167cSStefan Roese 1212554167cSStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 1222554167cSStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 1232554167cSStefan Roese 1242554167cSStefan Roese #define CONFIG_SPL_LIBCOMMON_SUPPORT 1252554167cSStefan Roese #define CONFIG_SPL_LIBGENERIC_SUPPORT 1262554167cSStefan Roese #define CONFIG_SPL_SERIAL_SUPPORT 1272554167cSStefan Roese #define CONFIG_SPL_I2C_SUPPORT 1282554167cSStefan Roese 1292554167cSStefan Roese /* SPL related SPI defines */ 1302554167cSStefan Roese #define CONFIG_SPL_SPI_SUPPORT 1312554167cSStefan Roese #define CONFIG_SPL_SPI_FLASH_SUPPORT 1322554167cSStefan Roese #define CONFIG_SPL_SPI_LOAD 1332554167cSStefan Roese #define CONFIG_SPL_SPI_BUS 0 1342554167cSStefan Roese #define CONFIG_SPL_SPI_CS 0 1352554167cSStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 1362bd8711eSStefan Roese #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 1372554167cSStefan Roese 1382554167cSStefan Roese /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 139ff9112dfSStefan Roese #define CONFIG_SYS_MVEBU_DDR_AXP 1402554167cSStefan Roese #define CONFIG_SPD_EEPROM 0x4e 1412554167cSStefan Roese 142dd580801SStefan Roese #endif /* _CONFIG_DB_MV7846MP_GP_H */ 143