1dd580801SStefan Roese /* 2c4be10b5SStefan Roese * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de> 3dd580801SStefan Roese * 4dd580801SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5dd580801SStefan Roese */ 6dd580801SStefan Roese 7dd580801SStefan Roese #ifndef _CONFIG_DB_MV7846MP_GP_H 8dd580801SStefan Roese #define _CONFIG_DB_MV7846MP_GP_H 9dd580801SStefan Roese 10dd580801SStefan Roese /* 11dd580801SStefan Roese * High Level Configuration Options (easy to change) 12dd580801SStefan Roese */ 132554167cSStefan Roese #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ 142554167cSStefan Roese 15dd580801SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 16dd580801SStefan Roese 172923c2d2SStefan Roese /* 182923c2d2SStefan Roese * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 192923c2d2SStefan Roese * for DDR ECC byte filling in the SPL before loading the main 202923c2d2SStefan Roese * U-Boot into it. 212923c2d2SStefan Roese */ 222923c2d2SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00800000 23dd580801SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 24dd580801SStefan Roese 25dd580801SStefan Roese /* I2C */ 26dd580801SStefan Roese #define CONFIG_SYS_I2C 27dd580801SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 28dd82242bSPaul Kocialkowski #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 29dd580801SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 30dd580801SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 31dd580801SStefan Roese 3249114c87SStefan Roese /* USB/EHCI configuration */ 3349114c87SStefan Roese #define CONFIG_EHCI_IS_TDI 348a333716SAnton Schubert #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 3549114c87SStefan Roese 36dd580801SStefan Roese /* SPI NOR flash default params, used by sf commands */ 37dd580801SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 38dd580801SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 39dd580801SStefan Roese 40dd580801SStefan Roese /* Environment in SPI NOR flash */ 41dd580801SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 42dd580801SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 43dd580801SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 44dd580801SStefan Roese 45dd580801SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 46dd580801SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 47dd580801SStefan Roese 48dd580801SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 49dd580801SStefan Roese 50e863f7f0SAnton Schubert /* SATA support */ 51c4be10b5SStefan Roese #define CONFIG_SYS_SATA_MAX_DEVICE 2 52c4be10b5SStefan Roese #define CONFIG_SATA_MV 53c4be10b5SStefan Roese #define CONFIG_LIBATA 54c4be10b5SStefan Roese #define CONFIG_LBA48 55e863f7f0SAnton Schubert 568c822825SStefan Roese /* Additional FS support/configuration */ 578c822825SStefan Roese #define CONFIG_SUPPORT_VFAT 588c822825SStefan Roese 5941e705acSStefan Roese /* PCIe support */ 606451223aSStefan Roese #ifndef CONFIG_SPL_BUILD 6141e705acSStefan Roese #define CONFIG_PCI_MVEBU 6241e705acSStefan Roese #define CONFIG_PCI_SCAN_SHOW 636451223aSStefan Roese #endif 6441e705acSStefan Roese 65d6b6303dSStefan Roese /* NAND */ 66d6b6303dSStefan Roese #define CONFIG_SYS_NAND_USE_FLASH_BBT 67d6b6303dSStefan Roese #define CONFIG_SYS_NAND_ONFI_DETECTION 68d6b6303dSStefan Roese 69dd580801SStefan Roese /* 70dd580801SStefan Roese * mv-common.h should be defined after CMD configs since it used them 71dd580801SStefan Roese * to enable certain macros 72dd580801SStefan Roese */ 73dd580801SStefan Roese #include "mv-common.h" 74dd580801SStefan Roese 752554167cSStefan Roese /* 762554167cSStefan Roese * Memory layout while starting into the bin_hdr via the 772554167cSStefan Roese * BootROM: 782554167cSStefan Roese * 792554167cSStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 802554167cSStefan Roese * 0x4000.4030 bin_hdr start address 812554167cSStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 822554167cSStefan Roese * 0x4007.fffc BootROM stack top 832554167cSStefan Roese * 842554167cSStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 852554167cSStefan Roese * L2 cache thus cannot be used. 862554167cSStefan Roese */ 872554167cSStefan Roese 882554167cSStefan Roese /* SPL */ 892554167cSStefan Roese /* Defines for SPL */ 902554167cSStefan Roese #define CONFIG_SPL_FRAMEWORK 912554167cSStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 922554167cSStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 932554167cSStefan Roese 942554167cSStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 952554167cSStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 962554167cSStefan Roese 976451223aSStefan Roese #ifdef CONFIG_SPL_BUILD 986451223aSStefan Roese #define CONFIG_SYS_MALLOC_SIMPLE 996451223aSStefan Roese #endif 1002554167cSStefan Roese 1012554167cSStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 1022554167cSStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 1032554167cSStefan Roese 1042554167cSStefan Roese /* SPL related SPI defines */ 1052554167cSStefan Roese #define CONFIG_SPL_SPI_LOAD 1062554167cSStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 1072bd8711eSStefan Roese #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 1082554167cSStefan Roese 1092554167cSStefan Roese /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 1102554167cSStefan Roese #define CONFIG_SPD_EEPROM 0x4e 111*698ffab2SStefan Roese #define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ 1122554167cSStefan Roese 113dd580801SStefan Roese #endif /* _CONFIG_DB_MV7846MP_GP_H */ 114