1 /* 2 * Copyright (C) 2014 Stefan Roese <sr@denx.de> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _CONFIG_DB_88F6820_GP_H 8 #define _CONFIG_DB_88F6820_GP_H 9 10 /* 11 * High Level Configuration Options (easy to change) 12 */ 13 #define CONFIG_ARMADA_XP /* SOC Family Name */ 14 #define CONFIG_ARMADA_38X 15 #define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ 16 17 #define CONFIG_SYS_L2_PL310 18 19 #ifdef CONFIG_SPL_BUILD 20 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 21 #endif 22 #define CONFIG_SYS_GENERIC_BOARD 23 #define CONFIG_DISPLAY_BOARDINFO_LATE 24 25 /* 26 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 27 * for DDR ECC byte filling in the SPL before loading the main 28 * U-Boot into it. 29 */ 30 #define CONFIG_SYS_TEXT_BASE 0x00800000 31 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 32 33 /* 34 * Commands configuration 35 */ 36 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 37 #define CONFIG_CMD_CACHE 38 #define CONFIG_CMD_DHCP 39 #define CONFIG_CMD_ENV 40 #define CONFIG_CMD_EXT2 41 #define CONFIG_CMD_EXT4 42 #define CONFIG_CMD_FAT 43 #define CONFIG_CMD_FS_GENERIC 44 #define CONFIG_CMD_I2C 45 #define CONFIG_CMD_MMC 46 #define CONFIG_CMD_PCI 47 #define CONFIG_CMD_PING 48 #define CONFIG_CMD_SCSI 49 #define CONFIG_CMD_SF 50 #define CONFIG_CMD_SPI 51 #define CONFIG_CMD_TFTPPUT 52 #define CONFIG_CMD_TIME 53 #define CONFIG_CMD_USB 54 55 /* I2C */ 56 #define CONFIG_SYS_I2C 57 #define CONFIG_SYS_I2C_MVTWSI 58 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 59 #define CONFIG_SYS_I2C_SLAVE 0x0 60 #define CONFIG_SYS_I2C_SPEED 100000 61 62 /* SPI NOR flash default params, used by sf commands */ 63 #define CONFIG_SF_DEFAULT_SPEED 1000000 64 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 65 #define CONFIG_SPI_FLASH_STMICRO 66 67 /* 68 * SDIO/MMC Card Configuration 69 */ 70 #define CONFIG_MMC 71 #define CONFIG_MMC_SDMA 72 #define CONFIG_GENERIC_MMC 73 #define CONFIG_SDHCI 74 #define CONFIG_MV_SDHCI 75 #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE 76 77 /* 78 * SATA/SCSI/AHCI configuration 79 */ 80 #define CONFIG_LIBATA 81 #define CONFIG_SCSI_AHCI 82 #define CONFIG_SCSI_AHCI_PLAT 83 #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 84 #define CONFIG_SYS_SCSI_MAX_LUN 1 85 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 86 CONFIG_SYS_SCSI_MAX_LUN) 87 88 /* Partition support */ 89 #define CONFIG_DOS_PARTITION 90 #define CONFIG_EFI_PARTITION 91 92 /* Additional FS support/configuration */ 93 #define CONFIG_SUPPORT_VFAT 94 95 /* USB/EHCI configuration */ 96 #define CONFIG_USB_EHCI 97 #define CONFIG_USB_STORAGE 98 #define CONFIG_USB_EHCI_MARVELL 99 #define CONFIG_EHCI_IS_TDI 100 101 /* Environment in SPI NOR flash */ 102 #define CONFIG_ENV_IS_IN_SPI_FLASH 103 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 104 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 105 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 106 107 #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 108 #define CONFIG_PHY_ADDR { 1, 0 } 109 #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII 110 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 111 112 /* PCIe support */ 113 #define CONFIG_PCI 114 #define CONFIG_PCI_MVEBU 115 #define CONFIG_PCI_PNP 116 #define CONFIG_PCI_SCAN_SHOW 117 #define CONFIG_E1000 /* enable Intel E1000 support for testing */ 118 119 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 120 #define CONFIG_SYS_ALT_MEMTEST 121 122 /* Keep device tree and initrd in lower memory so the kernel can access them */ 123 #define CONFIG_EXTRA_ENV_SETTINGS \ 124 "fdt_high=0x10000000\0" \ 125 "initrd_high=0x10000000\0" 126 127 /* SPL */ 128 /* 129 * Select the boot device here 130 * 131 * Currently supported are: 132 * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash 133 * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) 134 */ 135 #define SPL_BOOT_SPI_NOR_FLASH 1 136 #define SPL_BOOT_SDIO_MMC_CARD 2 137 #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH 138 139 /* Defines for SPL */ 140 #define CONFIG_SPL_FRAMEWORK 141 #define CONFIG_SPL_SIZE (140 << 10) 142 #define CONFIG_SPL_TEXT_BASE 0x40000030 143 #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) 144 145 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) 146 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 147 148 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 149 CONFIG_SPL_BSS_MAX_SIZE) 150 #define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) 151 152 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 153 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 154 155 #define CONFIG_SPL_LIBCOMMON_SUPPORT 156 #define CONFIG_SPL_LIBGENERIC_SUPPORT 157 #define CONFIG_SPL_SERIAL_SUPPORT 158 #define CONFIG_SPL_I2C_SUPPORT 159 160 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH 161 /* SPL related SPI defines */ 162 #define CONFIG_SPL_SPI_SUPPORT 163 #define CONFIG_SPL_SPI_FLASH_SUPPORT 164 #define CONFIG_SPL_SPI_LOAD 165 #define CONFIG_SPL_SPI_BUS 0 166 #define CONFIG_SPL_SPI_CS 0 167 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 168 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 169 #endif 170 171 #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD 172 /* SPL related MMC defines */ 173 #define CONFIG_SPL_MMC_SUPPORT 174 #define CONFIG_SPL_LIBDISK_SUPPORT 175 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 176 #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) 177 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS 178 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) 179 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS ((512 << 10) / 512) /* 512KiB */ 180 #ifdef CONFIG_SPL_BUILD 181 #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ 182 #endif 183 #endif 184 185 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 186 #define CONFIG_SYS_MVEBU_DDR_A38X 187 #define CONFIG_DDR3 188 189 /* 190 * mv-common.h should be defined after CMD configs since it used them 191 * to enable certain macros 192 */ 193 #include "mv-common.h" 194 195 #endif /* _CONFIG_DB_88F6820_GP_H */ 196