12bae75a4SStefan Roese /* 22bae75a4SStefan Roese * Copyright (C) 2014 Stefan Roese <sr@denx.de> 32bae75a4SStefan Roese * 42bae75a4SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 52bae75a4SStefan Roese */ 62bae75a4SStefan Roese 72bae75a4SStefan Roese #ifndef _CONFIG_DB_88F6820_GP_H 82bae75a4SStefan Roese #define _CONFIG_DB_88F6820_GP_H 92bae75a4SStefan Roese 102bae75a4SStefan Roese /* 112bae75a4SStefan Roese * High Level Configuration Options (easy to change) 122bae75a4SStefan Roese */ 132bae75a4SStefan Roese #define CONFIG_ARMADA_XP /* SOC Family Name */ 14*9e30b31dSStefan Roese #define CONFIG_ARMADA_38X 152bae75a4SStefan Roese #define CONFIG_DB_88F6820_GP /* Board target name for DDR training */ 162bae75a4SStefan Roese 172bae75a4SStefan Roese #define CONFIG_SYS_L2_PL310 182bae75a4SStefan Roese 192bae75a4SStefan Roese #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ 202bae75a4SStefan Roese #define CONFIG_SYS_GENERIC_BOARD 212bae75a4SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 222bae75a4SStefan Roese 232bae75a4SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x04000000 242bae75a4SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 252bae75a4SStefan Roese 262bae75a4SStefan Roese /* 272bae75a4SStefan Roese * Commands configuration 282bae75a4SStefan Roese */ 292bae75a4SStefan Roese #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */ 302bae75a4SStefan Roese #define CONFIG_CMD_CACHE 312bae75a4SStefan Roese #define CONFIG_CMD_DHCP 322bae75a4SStefan Roese #define CONFIG_CMD_ENV 33e80f1e85SStefan Roese #define CONFIG_CMD_EXT2 34e80f1e85SStefan Roese #define CONFIG_CMD_EXT4 35e80f1e85SStefan Roese #define CONFIG_CMD_FAT 36e80f1e85SStefan Roese #define CONFIG_CMD_FS_GENERIC 372bae75a4SStefan Roese #define CONFIG_CMD_I2C 38e80f1e85SStefan Roese #define CONFIG_CMD_MMC 392bae75a4SStefan Roese #define CONFIG_CMD_PING 404d991cb3SStefan Roese #define CONFIG_CMD_SCSI 412bae75a4SStefan Roese #define CONFIG_CMD_SF 422bae75a4SStefan Roese #define CONFIG_CMD_SPI 432bae75a4SStefan Roese #define CONFIG_CMD_TFTPPUT 442bae75a4SStefan Roese #define CONFIG_CMD_TIME 4559565736SStefan Roese #define CONFIG_CMD_USB 462bae75a4SStefan Roese 472bae75a4SStefan Roese /* I2C */ 482bae75a4SStefan Roese #define CONFIG_SYS_I2C 492bae75a4SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 502bae75a4SStefan Roese #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 512bae75a4SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 522bae75a4SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 532bae75a4SStefan Roese 542bae75a4SStefan Roese /* SPI NOR flash default params, used by sf commands */ 552bae75a4SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 562bae75a4SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 572bae75a4SStefan Roese #define CONFIG_SPI_FLASH_STMICRO 582bae75a4SStefan Roese 59e80f1e85SStefan Roese /* 60e80f1e85SStefan Roese * SDIO/MMC Card Configuration 61e80f1e85SStefan Roese */ 62e80f1e85SStefan Roese #define CONFIG_MMC 63e80f1e85SStefan Roese #define CONFIG_MMC_SDMA 64e80f1e85SStefan Roese #define CONFIG_GENERIC_MMC 65e80f1e85SStefan Roese #define CONFIG_SDHCI 66e80f1e85SStefan Roese #define CONFIG_MV_SDHCI 67e80f1e85SStefan Roese #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE 68e80f1e85SStefan Roese 697cbaff95SStefan Roese /* 707cbaff95SStefan Roese * SATA/SCSI/AHCI configuration 717cbaff95SStefan Roese */ 727cbaff95SStefan Roese #define CONFIG_LIBATA 737cbaff95SStefan Roese #define CONFIG_SCSI_AHCI 747cbaff95SStefan Roese #define CONFIG_SCSI_AHCI_PLAT 757cbaff95SStefan Roese #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 767cbaff95SStefan Roese #define CONFIG_SYS_SCSI_MAX_LUN 1 777cbaff95SStefan Roese #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 787cbaff95SStefan Roese CONFIG_SYS_SCSI_MAX_LUN) 797cbaff95SStefan Roese 80e80f1e85SStefan Roese /* Partition support */ 81e80f1e85SStefan Roese #define CONFIG_DOS_PARTITION 82e80f1e85SStefan Roese #define CONFIG_EFI_PARTITION 83e80f1e85SStefan Roese 84e80f1e85SStefan Roese /* Additional FS support/configuration */ 85e80f1e85SStefan Roese #define CONFIG_SUPPORT_VFAT 86e80f1e85SStefan Roese 8759565736SStefan Roese /* USB/EHCI configuration */ 8859565736SStefan Roese #define CONFIG_USB_EHCI 8959565736SStefan Roese #define CONFIG_USB_STORAGE 9059565736SStefan Roese #define CONFIG_USB_EHCI_MARVELL 9159565736SStefan Roese #define CONFIG_EHCI_IS_TDI 9259565736SStefan Roese 932bae75a4SStefan Roese /* Environment in SPI NOR flash */ 942bae75a4SStefan Roese #define CONFIG_ENV_IS_IN_SPI_FLASH 952bae75a4SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 962bae75a4SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 972bae75a4SStefan Roese #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 982bae75a4SStefan Roese 992bae75a4SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 1002bae75a4SStefan Roese #define CONFIG_PHY_ADDR { 1, 0 } 1012bae75a4SStefan Roese #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII 1022bae75a4SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 1032bae75a4SStefan Roese 1042bae75a4SStefan Roese #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */ 1052bae75a4SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 1062bae75a4SStefan Roese 1073fd38af7SKevin Smith /* Keep device tree and initrd in lower memory so the kernel can access them */ 1083fd38af7SKevin Smith #define CONFIG_EXTRA_ENV_SETTINGS \ 1093fd38af7SKevin Smith "fdt_high=0x10000000\0" \ 1103fd38af7SKevin Smith "initrd_high=0x10000000\0" 1113fd38af7SKevin Smith 112*9e30b31dSStefan Roese /* SPL */ 113*9e30b31dSStefan Roese /* Defines for SPL */ 114*9e30b31dSStefan Roese #define CONFIG_SPL_FRAMEWORK 115*9e30b31dSStefan Roese #define CONFIG_SPL_SIZE (140 << 10) 116*9e30b31dSStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40000030 117*9e30b31dSStefan Roese #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) 118*9e30b31dSStefan Roese 119*9e30b31dSStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) 120*9e30b31dSStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 121*9e30b31dSStefan Roese 122*9e30b31dSStefan Roese #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 123*9e30b31dSStefan Roese CONFIG_SPL_BSS_MAX_SIZE) 124*9e30b31dSStefan Roese #define CONFIG_SYS_SPL_MALLOC_SIZE (16 << 10) 125*9e30b31dSStefan Roese 126*9e30b31dSStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 127*9e30b31dSStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 128*9e30b31dSStefan Roese 129*9e30b31dSStefan Roese #define CONFIG_SPL_LIBCOMMON_SUPPORT 130*9e30b31dSStefan Roese #define CONFIG_SPL_LIBGENERIC_SUPPORT 131*9e30b31dSStefan Roese #define CONFIG_SPL_SERIAL_SUPPORT 132*9e30b31dSStefan Roese #define CONFIG_SPL_I2C_SUPPORT 133*9e30b31dSStefan Roese 134*9e30b31dSStefan Roese /* SPL related SPI defines */ 135*9e30b31dSStefan Roese #define CONFIG_SPL_SPI_SUPPORT 136*9e30b31dSStefan Roese #define CONFIG_SPL_SPI_FLASH_SUPPORT 137*9e30b31dSStefan Roese #define CONFIG_SPL_SPI_LOAD 138*9e30b31dSStefan Roese #define CONFIG_SPL_SPI_BUS 0 139*9e30b31dSStefan Roese #define CONFIG_SPL_SPI_CS 0 140*9e30b31dSStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 141*9e30b31dSStefan Roese 142*9e30b31dSStefan Roese /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ 143*9e30b31dSStefan Roese #define CONFIG_SYS_MVEBU_DDR_A38X 144*9e30b31dSStefan Roese #define CONFIG_DDR3 145*9e30b31dSStefan Roese 1462bae75a4SStefan Roese /* 1472bae75a4SStefan Roese * mv-common.h should be defined after CMD configs since it used them 1482bae75a4SStefan Roese * to enable certain macros 1492bae75a4SStefan Roese */ 1502bae75a4SStefan Roese #include "mv-common.h" 1512bae75a4SStefan Roese 1522bae75a4SStefan Roese #endif /* _CONFIG_DB_88F6820_GP_H */ 153