12bae75a4SStefan Roese /* 22bae75a4SStefan Roese * Copyright (C) 2014 Stefan Roese <sr@denx.de> 32bae75a4SStefan Roese * 42bae75a4SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 52bae75a4SStefan Roese */ 62bae75a4SStefan Roese 72bae75a4SStefan Roese #ifndef _CONFIG_DB_88F6820_GP_H 82bae75a4SStefan Roese #define _CONFIG_DB_88F6820_GP_H 92bae75a4SStefan Roese 102bae75a4SStefan Roese /* 112bae75a4SStefan Roese * High Level Configuration Options (easy to change) 122bae75a4SStefan Roese */ 132bae75a4SStefan Roese 142bae75a4SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 152bae75a4SStefan Roese 162923c2d2SStefan Roese /* 172923c2d2SStefan Roese * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 182923c2d2SStefan Roese * for DDR ECC byte filling in the SPL before loading the main 192923c2d2SStefan Roese * U-Boot into it. 202923c2d2SStefan Roese */ 212923c2d2SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00800000 222bae75a4SStefan Roese #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ 232bae75a4SStefan Roese 242bae75a4SStefan Roese /* 252bae75a4SStefan Roese * Commands configuration 262bae75a4SStefan Roese */ 272bae75a4SStefan Roese 282bae75a4SStefan Roese /* I2C */ 292bae75a4SStefan Roese #define CONFIG_SYS_I2C 302bae75a4SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 312bae75a4SStefan Roese #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 322bae75a4SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 332bae75a4SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 342bae75a4SStefan Roese 352bae75a4SStefan Roese /* SPI NOR flash default params, used by sf commands */ 362bae75a4SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 372bae75a4SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 382bae75a4SStefan Roese 39e80f1e85SStefan Roese /* 40e80f1e85SStefan Roese * SDIO/MMC Card Configuration 41e80f1e85SStefan Roese */ 42e80f1e85SStefan Roese #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE 43e80f1e85SStefan Roese 447cbaff95SStefan Roese /* 457cbaff95SStefan Roese * SATA/SCSI/AHCI configuration 467cbaff95SStefan Roese */ 477cbaff95SStefan Roese #define CONFIG_LIBATA 487cbaff95SStefan Roese #define CONFIG_SCSI_AHCI 497cbaff95SStefan Roese #define CONFIG_SCSI_AHCI_PLAT 507cbaff95SStefan Roese #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 517cbaff95SStefan Roese #define CONFIG_SYS_SCSI_MAX_LUN 1 527cbaff95SStefan Roese #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ 537cbaff95SStefan Roese CONFIG_SYS_SCSI_MAX_LUN) 547cbaff95SStefan Roese 55e80f1e85SStefan Roese /* Partition support */ 56e80f1e85SStefan Roese 57e80f1e85SStefan Roese /* Additional FS support/configuration */ 58e80f1e85SStefan Roese #define CONFIG_SUPPORT_VFAT 59e80f1e85SStefan Roese 6059565736SStefan Roese /* USB/EHCI configuration */ 6159565736SStefan Roese #define CONFIG_EHCI_IS_TDI 6259565736SStefan Roese 632bae75a4SStefan Roese /* Environment in SPI NOR flash */ 642bae75a4SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 652bae75a4SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 662bae75a4SStefan Roese #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ 672bae75a4SStefan Roese 682bae75a4SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 692bae75a4SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 702bae75a4SStefan Roese 71ce2cb1d3SStefan Roese /* PCIe support */ 726451223aSStefan Roese #ifndef CONFIG_SPL_BUILD 73ce2cb1d3SStefan Roese #define CONFIG_PCI_MVEBU 74ce2cb1d3SStefan Roese #define CONFIG_PCI_SCAN_SHOW 756451223aSStefan Roese #endif 76ce2cb1d3SStefan Roese 772bae75a4SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 782bae75a4SStefan Roese 793fd38af7SKevin Smith /* Keep device tree and initrd in lower memory so the kernel can access them */ 803fd38af7SKevin Smith #define CONFIG_EXTRA_ENV_SETTINGS \ 813fd38af7SKevin Smith "fdt_high=0x10000000\0" \ 823fd38af7SKevin Smith "initrd_high=0x10000000\0" 833fd38af7SKevin Smith 849e30b31dSStefan Roese /* SPL */ 857853c508SStefan Roese /* 867853c508SStefan Roese * Select the boot device here 877853c508SStefan Roese * 887853c508SStefan Roese * Currently supported are: 897853c508SStefan Roese * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash 907853c508SStefan Roese * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) 917853c508SStefan Roese */ 927853c508SStefan Roese #define SPL_BOOT_SPI_NOR_FLASH 1 937853c508SStefan Roese #define SPL_BOOT_SDIO_MMC_CARD 2 947853c508SStefan Roese #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH 957853c508SStefan Roese 969e30b31dSStefan Roese /* Defines for SPL */ 979e30b31dSStefan Roese #define CONFIG_SPL_FRAMEWORK 989e30b31dSStefan Roese #define CONFIG_SPL_SIZE (140 << 10) 999e30b31dSStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40000030 1009e30b31dSStefan Roese #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x0030) 1019e30b31dSStefan Roese 1029e30b31dSStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) 1039e30b31dSStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 1049e30b31dSStefan Roese 1056451223aSStefan Roese #ifdef CONFIG_SPL_BUILD 1066451223aSStefan Roese #define CONFIG_SYS_MALLOC_SIMPLE 1076451223aSStefan Roese #endif 1089e30b31dSStefan Roese 1099e30b31dSStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 1109e30b31dSStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 1119e30b31dSStefan Roese 1127853c508SStefan Roese #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH 1139e30b31dSStefan Roese /* SPL related SPI defines */ 1149e30b31dSStefan Roese #define CONFIG_SPL_SPI_LOAD 115*09a54c00SStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x24000 1167853c508SStefan Roese #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 1177853c508SStefan Roese #endif 1187853c508SStefan Roese 1197853c508SStefan Roese #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD 1207853c508SStefan Roese /* SPL related MMC defines */ 1217853c508SStefan Roese #define CONFIG_SYS_MMC_U_BOOT_OFFS (160 << 10) 1227853c508SStefan Roese #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS 1237853c508SStefan Roese #ifdef CONFIG_SPL_BUILD 1247853c508SStefan Roese #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ 1257853c508SStefan Roese #endif 1267853c508SStefan Roese #endif 1279e30b31dSStefan Roese 1282bae75a4SStefan Roese /* 1292bae75a4SStefan Roese * mv-common.h should be defined after CMD configs since it used them 1302bae75a4SStefan Roese * to enable certain macros 1312bae75a4SStefan Roese */ 1322bae75a4SStefan Roese #include "mv-common.h" 1332bae75a4SStefan Roese 1342bae75a4SStefan Roese #endif /* _CONFIG_DB_88F6820_GP_H */ 135