1*606576d5SStefan Roese /* 2*606576d5SStefan Roese * Copyright (C) 2016 Stefan Roese <sr@denx.de> 3*606576d5SStefan Roese * 4*606576d5SStefan Roese * SPDX-License-Identifier: GPL-2.0+ 5*606576d5SStefan Roese */ 6*606576d5SStefan Roese 7*606576d5SStefan Roese #ifndef _CONFIG_DB_88F6720_H 8*606576d5SStefan Roese #define _CONFIG_DB_88F6720_H 9*606576d5SStefan Roese 10*606576d5SStefan Roese /* 11*606576d5SStefan Roese * High Level Configuration Options (easy to change) 12*606576d5SStefan Roese */ 13*606576d5SStefan Roese #define CONFIG_DISPLAY_BOARDINFO_LATE 14*606576d5SStefan Roese 15*606576d5SStefan Roese /* 16*606576d5SStefan Roese * TEXT_BASE needs to be below 16MiB, since this area is scrubbed 17*606576d5SStefan Roese * for DDR ECC byte filling in the SPL before loading the main 18*606576d5SStefan Roese * U-Boot into it. 19*606576d5SStefan Roese */ 20*606576d5SStefan Roese #define CONFIG_SYS_TEXT_BASE 0x00800000 21*606576d5SStefan Roese #define CONFIG_SYS_TCLK 200000000 /* 200MHz */ 22*606576d5SStefan Roese 23*606576d5SStefan Roese /* 24*606576d5SStefan Roese * Commands configuration 25*606576d5SStefan Roese */ 26*606576d5SStefan Roese 27*606576d5SStefan Roese /* I2C */ 28*606576d5SStefan Roese #define CONFIG_SYS_I2C 29*606576d5SStefan Roese #define CONFIG_SYS_I2C_MVTWSI 30*606576d5SStefan Roese #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE 31*606576d5SStefan Roese #define CONFIG_SYS_I2C_SLAVE 0x0 32*606576d5SStefan Roese #define CONFIG_SYS_I2C_SPEED 100000 33*606576d5SStefan Roese 34*606576d5SStefan Roese /* USB/EHCI configuration */ 35*606576d5SStefan Roese #define CONFIG_EHCI_IS_TDI 36*606576d5SStefan Roese #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 37*606576d5SStefan Roese 38*606576d5SStefan Roese /* SPI NOR flash default params, used by sf commands */ 39*606576d5SStefan Roese #define CONFIG_SF_DEFAULT_SPEED 1000000 40*606576d5SStefan Roese #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 41*606576d5SStefan Roese 42*606576d5SStefan Roese /* Environment in SPI NOR flash */ 43*606576d5SStefan Roese #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ 44*606576d5SStefan Roese #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ 45*606576d5SStefan Roese #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */ 46*606576d5SStefan Roese 47*606576d5SStefan Roese #define CONFIG_PHY_MARVELL /* there is a marvell phy */ 48*606576d5SStefan Roese #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ 49*606576d5SStefan Roese 50*606576d5SStefan Roese #define CONFIG_SYS_ALT_MEMTEST 51*606576d5SStefan Roese 52*606576d5SStefan Roese /* Additional FS support/configuration */ 53*606576d5SStefan Roese #define CONFIG_SUPPORT_VFAT 54*606576d5SStefan Roese 55*606576d5SStefan Roese /* 56*606576d5SStefan Roese * mv-common.h should be defined after CMD configs since it used them 57*606576d5SStefan Roese * to enable certain macros 58*606576d5SStefan Roese */ 59*606576d5SStefan Roese #include "mv-common.h" 60*606576d5SStefan Roese 61*606576d5SStefan Roese /* 62*606576d5SStefan Roese * Memory layout while starting into the bin_hdr via the 63*606576d5SStefan Roese * BootROM: 64*606576d5SStefan Roese * 65*606576d5SStefan Roese * 0x4000.4000 - 0x4003.4000 headers space (192KiB) 66*606576d5SStefan Roese * 0x4000.4030 bin_hdr start address 67*606576d5SStefan Roese * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) 68*606576d5SStefan Roese * 0x4007.fffc BootROM stack top 69*606576d5SStefan Roese * 70*606576d5SStefan Roese * The address space between 0x4007.fffc and 0x400f.fff is not locked in 71*606576d5SStefan Roese * L2 cache thus cannot be used. 72*606576d5SStefan Roese */ 73*606576d5SStefan Roese 74*606576d5SStefan Roese /* SPL */ 75*606576d5SStefan Roese /* Defines for SPL */ 76*606576d5SStefan Roese #define CONFIG_SPL_FRAMEWORK 77*606576d5SStefan Roese #define CONFIG_SPL_TEXT_BASE 0x40004030 78*606576d5SStefan Roese #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) 79*606576d5SStefan Roese 80*606576d5SStefan Roese #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) 81*606576d5SStefan Roese #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) 82*606576d5SStefan Roese 83*606576d5SStefan Roese #ifdef CONFIG_SPL_BUILD 84*606576d5SStefan Roese #define CONFIG_SYS_MALLOC_SIMPLE 85*606576d5SStefan Roese #endif 86*606576d5SStefan Roese 87*606576d5SStefan Roese #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) 88*606576d5SStefan Roese #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) 89*606576d5SStefan Roese 90*606576d5SStefan Roese /* SPL related SPI defines */ 91*606576d5SStefan Roese #define CONFIG_SPL_SPI_LOAD 92*606576d5SStefan Roese #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 93*606576d5SStefan Roese #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS 94*606576d5SStefan Roese 95*606576d5SStefan Roese #endif /* _CONFIG_DB_88F6720_H */ 96