1 /* 2 * Based on corenet_ds.h 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef __CONFIG_H 8 #define __CONFIG_H 9 10 #define CONFIG_CYRUS 11 12 #if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) 13 #error Must call Cyrus CONFIG with a specific CPU enabled. 14 #endif 15 16 #define CONFIG_SDCARD 17 #define CONFIG_FSL_SATA_V2 18 #define CONFIG_PCIE3 19 #define CONFIG_PCIE4 20 #ifdef CONFIG_ARCH_P5020 21 #define CONFIG_SYS_FSL_RAID_ENGINE 22 #define CONFIG_SYS_DPAA_RMAN 23 #endif 24 #define CONFIG_SYS_DPAA_PME 25 26 /* 27 * Corenet DS style board configuration file 28 */ 29 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 30 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 31 #define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg 32 #if defined(CONFIG_ARCH_P5020) 33 #define CONFIG_SYS_CLK_FREQ 133000000 34 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg 35 #elif defined(CONFIG_ARCH_P5040) 36 #define CONFIG_SYS_CLK_FREQ 100000000 37 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg 38 #endif 39 40 /* High Level Configuration Options */ 41 #define CONFIG_BOOKE 42 #define CONFIG_E500 /* BOOKE e500 family */ 43 #define CONFIG_E500MC /* BOOKE e500mc family */ 44 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 45 #define CONFIG_MP /* support multiple processors */ 46 47 #define CONFIG_SYS_MMC_MAX_DEVICE 1 48 49 #ifndef CONFIG_SYS_TEXT_BASE 50 #define CONFIG_SYS_TEXT_BASE 0xeff40000 51 #endif 52 53 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 54 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 55 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 56 #define CONFIG_PCIE1 /* PCIE controller 1 */ 57 #define CONFIG_PCIE2 /* PCIE controller 2 */ 58 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 59 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 60 61 #define CONFIG_ENV_OVERWRITE 62 63 #define CONFIG_SYS_NO_FLASH 64 65 #if defined(CONFIG_SDCARD) 66 #define CONFIG_SYS_EXTRA_ENV_RELOC 67 #define CONFIG_ENV_IS_IN_MMC 68 #define CONFIG_FSL_FIXED_MMC_LOCATION 69 #define CONFIG_SYS_MMC_ENV_DEV 0 70 #define CONFIG_ENV_SIZE 0x2000 71 #define CONFIG_ENV_OFFSET (512 * 1658) 72 #endif 73 74 /* 75 * These can be toggled for performance analysis, otherwise use default. 76 */ 77 #define CONFIG_SYS_CACHE_STASHING 78 #define CONFIG_BACKSIDE_L2_CACHE 79 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 80 #define CONFIG_BTB /* toggle branch predition */ 81 #define CONFIG_DDR_ECC 82 #ifdef CONFIG_DDR_ECC 83 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 84 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 85 #endif 86 87 #define CONFIG_ENABLE_36BIT_PHYS 88 89 #ifdef CONFIG_PHYS_64BIT 90 #define CONFIG_ADDR_MAP 91 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 92 #endif 93 94 /* test POST memory test */ 95 #undef CONFIG_POST 96 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 97 #define CONFIG_SYS_MEMTEST_END 0x00400000 98 #define CONFIG_SYS_ALT_MEMTEST 99 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 100 101 /* 102 * Config the L3 Cache as L3 SRAM 103 */ 104 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 105 #ifdef CONFIG_PHYS_64BIT 106 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 107 #else 108 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 109 #endif 110 #define CONFIG_SYS_L3_SIZE (1024 << 10) 111 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 112 113 #ifdef CONFIG_PHYS_64BIT 114 #define CONFIG_SYS_DCSRBAR 0xf0000000 115 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 116 #endif 117 118 /* 119 * DDR Setup 120 */ 121 #define CONFIG_VERY_BIG_RAM 122 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 123 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 124 125 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 126 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 127 128 #define CONFIG_DDR_SPD 129 #define CONFIG_SYS_FSL_DDR3 130 131 #define CONFIG_SYS_SPD_BUS_NUM 1 132 #define SPD_EEPROM_ADDRESS1 0x51 133 #define SPD_EEPROM_ADDRESS2 0x52 134 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 135 136 /* 137 * Local Bus Definitions 138 */ 139 140 #define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */ 141 #ifdef CONFIG_PHYS_64BIT 142 #define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull 143 #else 144 #define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE 145 #endif 146 147 #define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */ 148 #ifdef CONFIG_PHYS_64BIT 149 #define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull 150 #else 151 #define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE 152 #endif 153 154 /* Set the local bus clock 1/16 of platform clock */ 155 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1) 156 157 #define CONFIG_SYS_BR0_PRELIM \ 158 (BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V) 159 #define CONFIG_SYS_BR1_PRELIM \ 160 (BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V) 161 162 #define CONFIG_SYS_OR0_PRELIM 0xfff00010 163 #define CONFIG_SYS_OR1_PRELIM 0xfff00010 164 165 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 166 167 #if defined(CONFIG_RAMBOOT_PBL) 168 #define CONFIG_SYS_RAMBOOT 169 #endif 170 171 #define CONFIG_BOARD_EARLY_INIT_F 172 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 173 #define CONFIG_MISC_INIT_R 174 175 #define CONFIG_HWCONFIG 176 177 /* define to use L1 as initial stack */ 178 #define CONFIG_L1_INIT_RAM 179 #define CONFIG_SYS_INIT_RAM_LOCK 180 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 181 #ifdef CONFIG_PHYS_64BIT 182 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 183 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 184 /* The assembler doesn't like typecast */ 185 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 186 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 187 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 188 #else 189 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 190 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 191 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 192 #endif 193 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 194 195 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 196 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 197 198 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 199 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 200 201 /* Serial Port - controlled on board with jumper J8 202 * open - index 2 203 * shorted - index 1 204 */ 205 #define CONFIG_CONS_INDEX 1 206 #define CONFIG_SYS_NS16550_SERIAL 207 #define CONFIG_SYS_NS16550_REG_SIZE 1 208 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 209 210 #define CONFIG_SYS_BAUDRATE_TABLE \ 211 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 212 213 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 214 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 215 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 216 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 217 218 /* I2C */ 219 #define CONFIG_SYS_I2C 220 #define CONFIG_SYS_I2C_FSL 221 #define CONFIG_I2C_MULTI_BUS 222 #define CONFIG_I2C_CMD_TREE 223 #define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */ 224 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 225 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 226 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */ 227 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 228 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 229 #define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */ 230 #define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F 231 #define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000 232 #define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */ 233 #define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F 234 #define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100 235 236 #define CONFIG_ID_EEPROM 237 #define CONFIG_SYS_I2C_EEPROM_NXID 238 #define CONFIG_SYS_EEPROM_BUS_NUM 0 239 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 240 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 241 242 #define CONFIG_SYS_I2C_GENERIC_MAC 243 #define CONFIG_SYS_I2C_MAC1_BUS 3 244 #define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57 245 #define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2 246 #define CONFIG_SYS_I2C_MAC2_BUS 0 247 #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 248 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa 249 250 #define CONFIG_CMD_DATE 1 251 #define CONFIG_RTC_MCP79411 1 252 #define CONFIG_SYS_RTC_BUS_NUM 3 253 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f 254 255 /* 256 * eSPI - Enhanced SPI 257 */ 258 259 /* 260 * General PCI 261 * Memory space is mapped 1-1, but I/O space must start from 0. 262 */ 263 264 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 265 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 266 #ifdef CONFIG_PHYS_64BIT 267 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 268 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 269 #else 270 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 271 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 272 #endif 273 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 274 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 275 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 276 #ifdef CONFIG_PHYS_64BIT 277 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 278 #else 279 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 280 #endif 281 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 282 283 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 284 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 285 #ifdef CONFIG_PHYS_64BIT 286 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 287 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 288 #else 289 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 290 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 291 #endif 292 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 293 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 294 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 295 #ifdef CONFIG_PHYS_64BIT 296 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 297 #else 298 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 299 #endif 300 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 301 302 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 303 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 304 #ifdef CONFIG_PHYS_64BIT 305 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 306 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 307 #else 308 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 309 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 310 #endif 311 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 312 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 313 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 314 #ifdef CONFIG_PHYS_64BIT 315 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 316 #else 317 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 318 #endif 319 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 320 321 /* controller 4, Base address 203000 */ 322 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 323 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 324 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 325 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 326 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 327 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 328 329 /* Qman/Bman */ 330 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 331 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 332 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 333 #ifdef CONFIG_PHYS_64BIT 334 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 335 #else 336 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 337 #endif 338 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 339 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 340 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 341 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 342 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 343 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 344 CONFIG_SYS_BMAN_CENA_SIZE) 345 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 346 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 347 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 348 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 349 #ifdef CONFIG_PHYS_64BIT 350 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 351 #else 352 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 353 #endif 354 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 355 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 356 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 357 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 358 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 359 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 360 CONFIG_SYS_QMAN_CENA_SIZE) 361 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 362 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 363 364 #define CONFIG_SYS_DPAA_FMAN 365 /* Default address of microcode for the Linux Fman driver */ 366 /* 367 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 368 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 369 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 370 */ 371 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 372 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 373 374 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 375 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 376 377 #ifdef CONFIG_SYS_DPAA_FMAN 378 #define CONFIG_FMAN_ENET 379 #define CONFIG_PHY_MICREL 380 #define CONFIG_PHY_MICREL_KSZ9021 381 #endif 382 383 #ifdef CONFIG_PCI 384 #define CONFIG_PCI_INDIRECT_BRIDGE 385 #define CONFIG_NET_MULTI 386 387 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 388 #define CONFIG_DOS_PARTITION 389 #endif /* CONFIG_PCI */ 390 391 /* SATA */ 392 #ifdef CONFIG_FSL_SATA_V2 393 #define CONFIG_LIBATA 394 #define CONFIG_FSL_SATA 395 396 #define CONFIG_SYS_SATA_MAX_DEVICE 2 397 #define CONFIG_SATA1 398 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 399 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 400 #define CONFIG_SATA2 401 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 402 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 403 404 #define CONFIG_LBA48 405 #define CONFIG_CMD_SATA 406 #define CONFIG_DOS_PARTITION 407 #endif 408 409 #ifdef CONFIG_FMAN_ENET 410 #define CONFIG_SYS_TBIPA_VALUE 8 411 #define CONFIG_MII /* MII PHY management */ 412 #define CONFIG_ETHPRIME "FM1@DTSEC4" 413 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 414 #endif 415 416 /* 417 * Environment 418 */ 419 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 420 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 421 422 /* 423 * Command line configuration. 424 */ 425 #define CONFIG_CMD_ERRATA 426 #define CONFIG_CMD_IRQ 427 #define CONFIG_CMD_REGINFO 428 429 #ifdef CONFIG_PCI 430 #define CONFIG_CMD_PCI 431 #endif 432 433 /* 434 * USB 435 */ 436 #define CONFIG_HAS_FSL_DR_USB 437 #define CONFIG_HAS_FSL_MPH_USB 438 439 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 440 #define CONFIG_USB_EHCI 441 #define CONFIG_USB_EHCI_FSL 442 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 443 #define CONFIG_EHCI_IS_TDI 444 #define CONFIG_SYS_USB_EVENT_POLL 445 /* _VIA_CONTROL_EP */ 446 #endif 447 448 #ifdef CONFIG_MMC 449 #define CONFIG_FSL_ESDHC 450 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 451 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 452 #define CONFIG_GENERIC_MMC 453 #define CONFIG_DOS_PARTITION 454 #endif 455 456 /* 457 * Miscellaneous configurable options 458 */ 459 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 460 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 461 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 462 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 463 #ifdef CONFIG_CMD_KGDB 464 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 465 #else 466 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 467 #endif 468 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 469 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 470 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 471 472 /* 473 * For booting Linux, the board info and command line data 474 * have to be in the first 64 MB of memory, since this is 475 * the maximum mapped by the Linux kernel during initialization. 476 */ 477 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 478 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 479 480 #ifdef CONFIG_CMD_KGDB 481 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 482 #endif 483 484 /* 485 * Environment Configuration 486 */ 487 #define CONFIG_ROOTPATH "/opt/nfsroot" 488 #define CONFIG_BOOTFILE "uImage" 489 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 490 491 /* default location for tftp and bootm */ 492 #define CONFIG_LOADADDR 1000000 493 494 495 #define CONFIG_BAUDRATE 115200 496 497 #define __USB_PHY_TYPE utmi 498 499 #define CONFIG_EXTRA_ENV_SETTINGS \ 500 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 501 "bank_intlv=cs0_cs1;" \ 502 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 503 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 504 "netdev=eth0\0" \ 505 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 506 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 507 "consoledev=ttyS0\0" \ 508 "ramdiskaddr=2000000\0" \ 509 "fdtaddr=1e00000\0" \ 510 "bdev=sda3\0" 511 512 #define CONFIG_HDBOOT \ 513 "setenv bootargs root=/dev/$bdev rw " \ 514 "console=$consoledev,$baudrate $othbootargs;" \ 515 "tftp $loadaddr $bootfile;" \ 516 "tftp $fdtaddr $fdtfile;" \ 517 "bootm $loadaddr - $fdtaddr" 518 519 #define CONFIG_NFSBOOTCOMMAND \ 520 "setenv bootargs root=/dev/nfs rw " \ 521 "nfsroot=$serverip:$rootpath " \ 522 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 523 "console=$consoledev,$baudrate $othbootargs;" \ 524 "tftp $loadaddr $bootfile;" \ 525 "tftp $fdtaddr $fdtfile;" \ 526 "bootm $loadaddr - $fdtaddr" 527 528 #define CONFIG_RAMBOOTCOMMAND \ 529 "setenv bootargs root=/dev/ram rw " \ 530 "console=$consoledev,$baudrate $othbootargs;" \ 531 "tftp $ramdiskaddr $ramdiskfile;" \ 532 "tftp $loadaddr $bootfile;" \ 533 "tftp $fdtaddr $fdtfile;" \ 534 "bootm $loadaddr $ramdiskaddr $fdtaddr" 535 536 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 537 538 #include <asm/fsl_secure_boot.h> 539 540 #ifdef CONFIG_SECURE_BOOT 541 #endif 542 543 #endif /* __CONFIG_H */ 544