1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #include "../board/freescale/common/ics307_clk.h" 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #define CONFIG_PBLPBI_CONFIG $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg 35 #if defined(CONFIG_P3041DS) 36 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg 37 #elif defined(CONFIG_P4080DS) 38 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg 39 #elif defined(CONFIG_P5020DS) 40 #define CONFIG_PBLRCW_CONFIG $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg 41 #endif 42 #endif 43 44 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 45 /* Set 1M boot space */ 46 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 47 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 48 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 49 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 50 #define CONFIG_SYS_NO_FLASH 51 #endif 52 53 /* High Level Configuration Options */ 54 #define CONFIG_BOOKE 55 #define CONFIG_E500 /* BOOKE e500 family */ 56 #define CONFIG_E500MC /* BOOKE e500mc family */ 57 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 58 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 59 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 60 #define CONFIG_MP /* support multiple processors */ 61 62 #ifndef CONFIG_SYS_TEXT_BASE 63 #define CONFIG_SYS_TEXT_BASE 0xeff80000 64 #endif 65 66 #ifndef CONFIG_RESET_VECTOR_ADDRESS 67 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 68 #endif 69 70 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 71 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 72 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 73 #define CONFIG_PCI /* Enable PCI/PCIE */ 74 #define CONFIG_PCIE1 /* PCIE controler 1 */ 75 #define CONFIG_PCIE2 /* PCIE controler 2 */ 76 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 77 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 78 79 #define CONFIG_SYS_SRIO 80 #define CONFIG_SRIO1 /* SRIO port 1 */ 81 #define CONFIG_SRIO2 /* SRIO port 2 */ 82 83 #define CONFIG_FSL_LAW /* Use common FSL init code */ 84 85 #define CONFIG_ENV_OVERWRITE 86 87 #ifdef CONFIG_SYS_NO_FLASH 88 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 89 #define CONFIG_ENV_IS_NOWHERE 90 #endif 91 #else 92 #define CONFIG_FLASH_CFI_DRIVER 93 #define CONFIG_SYS_FLASH_CFI 94 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 95 #endif 96 97 #if defined(CONFIG_SPIFLASH) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_ENV_IS_IN_SPI_FLASH 100 #define CONFIG_ENV_SPI_BUS 0 101 #define CONFIG_ENV_SPI_CS 0 102 #define CONFIG_ENV_SPI_MAX_HZ 10000000 103 #define CONFIG_ENV_SPI_MODE 0 104 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 105 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 106 #define CONFIG_ENV_SECT_SIZE 0x10000 107 #elif defined(CONFIG_SDCARD) 108 #define CONFIG_SYS_EXTRA_ENV_RELOC 109 #define CONFIG_ENV_IS_IN_MMC 110 #define CONFIG_FSL_FIXED_MMC_LOCATION 111 #define CONFIG_SYS_MMC_ENV_DEV 0 112 #define CONFIG_ENV_SIZE 0x2000 113 #define CONFIG_ENV_OFFSET (512 * 1097) 114 #elif defined(CONFIG_NAND) 115 #define CONFIG_SYS_EXTRA_ENV_RELOC 116 #define CONFIG_ENV_IS_IN_NAND 117 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 118 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 119 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 120 #define CONFIG_ENV_IS_IN_REMOTE 121 #define CONFIG_ENV_ADDR 0xffe20000 122 #define CONFIG_ENV_SIZE 0x2000 123 #elif defined(CONFIG_ENV_IS_NOWHERE) 124 #define CONFIG_ENV_SIZE 0x2000 125 #else 126 #define CONFIG_ENV_IS_IN_FLASH 127 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 128 #define CONFIG_ENV_SIZE 0x2000 129 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 130 #endif 131 132 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 133 134 /* 135 * These can be toggled for performance analysis, otherwise use default. 136 */ 137 #define CONFIG_SYS_CACHE_STASHING 138 #define CONFIG_BACKSIDE_L2_CACHE 139 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 140 #define CONFIG_BTB /* toggle branch predition */ 141 #define CONFIG_DDR_ECC 142 #ifdef CONFIG_DDR_ECC 143 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 144 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 145 #endif 146 147 #define CONFIG_ENABLE_36BIT_PHYS 148 149 #ifdef CONFIG_PHYS_64BIT 150 #define CONFIG_ADDR_MAP 151 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 152 #endif 153 154 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 155 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 156 #define CONFIG_SYS_MEMTEST_END 0x00400000 157 #define CONFIG_SYS_ALT_MEMTEST 158 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 159 160 /* 161 * Config the L3 Cache as L3 SRAM 162 */ 163 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 164 #ifdef CONFIG_PHYS_64BIT 165 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 166 #else 167 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 168 #endif 169 #define CONFIG_SYS_L3_SIZE (1024 << 10) 170 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 171 172 #ifdef CONFIG_PHYS_64BIT 173 #define CONFIG_SYS_DCSRBAR 0xf0000000 174 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 175 #endif 176 177 /* EEPROM */ 178 #define CONFIG_ID_EEPROM 179 #define CONFIG_SYS_I2C_EEPROM_NXID 180 #define CONFIG_SYS_EEPROM_BUS_NUM 0 181 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 182 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 183 184 /* 185 * DDR Setup 186 */ 187 #define CONFIG_VERY_BIG_RAM 188 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 189 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 190 191 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 192 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 193 194 #define CONFIG_DDR_SPD 195 #define CONFIG_FSL_DDR3 196 197 #ifdef CONFIG_P3060QDS 198 #define CONFIG_SYS_SPD_BUS_NUM 0 199 #else 200 #define CONFIG_SYS_SPD_BUS_NUM 1 201 #endif 202 #define SPD_EEPROM_ADDRESS1 0x51 203 #define SPD_EEPROM_ADDRESS2 0x52 204 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 205 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 206 207 /* 208 * Local Bus Definitions 209 */ 210 211 /* Set the local bus clock 1/8 of platform clock */ 212 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 213 214 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 215 #ifdef CONFIG_PHYS_64BIT 216 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 217 #else 218 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 219 #endif 220 221 #define CONFIG_SYS_FLASH_BR_PRELIM \ 222 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 223 | BR_PS_16 | BR_V) 224 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 225 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 226 227 #define CONFIG_SYS_BR1_PRELIM \ 228 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 229 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 230 231 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 232 #ifdef CONFIG_PHYS_64BIT 233 #define PIXIS_BASE_PHYS 0xfffdf0000ull 234 #else 235 #define PIXIS_BASE_PHYS PIXIS_BASE 236 #endif 237 238 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 239 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 240 241 #define PIXIS_LBMAP_SWITCH 7 242 #define PIXIS_LBMAP_MASK 0xf0 243 #define PIXIS_LBMAP_SHIFT 4 244 #define PIXIS_LBMAP_ALTBANK 0x40 245 246 #define CONFIG_SYS_FLASH_QUIET_TEST 247 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 248 249 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 250 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 251 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 252 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 253 254 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 255 256 #if defined(CONFIG_RAMBOOT_PBL) 257 #define CONFIG_SYS_RAMBOOT 258 #endif 259 260 /* Nand Flash */ 261 #ifdef CONFIG_NAND_FSL_ELBC 262 #define CONFIG_SYS_NAND_BASE 0xffa00000 263 #ifdef CONFIG_PHYS_64BIT 264 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 265 #else 266 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 267 #endif 268 269 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 270 #define CONFIG_SYS_MAX_NAND_DEVICE 1 271 #define CONFIG_MTD_NAND_VERIFY_WRITE 272 #define CONFIG_CMD_NAND 273 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 274 275 /* NAND flash config */ 276 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 277 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 278 | BR_PS_8 /* Port Size = 8 bit */ \ 279 | BR_MS_FCM /* MSEL = FCM */ \ 280 | BR_V) /* valid */ 281 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 282 | OR_FCM_PGS /* Large Page*/ \ 283 | OR_FCM_CSCT \ 284 | OR_FCM_CST \ 285 | OR_FCM_CHT \ 286 | OR_FCM_SCY_1 \ 287 | OR_FCM_TRLX \ 288 | OR_FCM_EHTR) 289 290 #ifdef CONFIG_NAND 291 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 292 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 293 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 294 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 295 #else 296 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 297 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 298 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 299 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 300 #endif 301 #else 302 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 303 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 304 #endif /* CONFIG_NAND_FSL_ELBC */ 305 306 #define CONFIG_SYS_FLASH_EMPTY_INFO 307 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 308 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 309 310 #define CONFIG_BOARD_EARLY_INIT_F 311 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 312 #define CONFIG_MISC_INIT_R 313 314 #define CONFIG_HWCONFIG 315 316 /* define to use L1 as initial stack */ 317 #define CONFIG_L1_INIT_RAM 318 #define CONFIG_SYS_INIT_RAM_LOCK 319 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 320 #ifdef CONFIG_PHYS_64BIT 321 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 322 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 323 /* The assembler doesn't like typecast */ 324 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 325 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 326 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 327 #else 328 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 329 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 330 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 331 #endif 332 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 333 334 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 335 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 336 337 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 338 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 339 340 /* Serial Port - controlled on board with jumper J8 341 * open - index 2 342 * shorted - index 1 343 */ 344 #define CONFIG_CONS_INDEX 1 345 #define CONFIG_SYS_NS16550 346 #define CONFIG_SYS_NS16550_SERIAL 347 #define CONFIG_SYS_NS16550_REG_SIZE 1 348 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 349 350 #define CONFIG_SYS_BAUDRATE_TABLE \ 351 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 352 353 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 354 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 355 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 356 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 357 358 /* Use the HUSH parser */ 359 #define CONFIG_SYS_HUSH_PARSER 360 361 /* pass open firmware flat tree */ 362 #define CONFIG_OF_LIBFDT 363 #define CONFIG_OF_BOARD_SETUP 364 #define CONFIG_OF_STDOUT_VIA_ALIAS 365 366 /* new uImage format support */ 367 #define CONFIG_FIT 368 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 369 370 /* I2C */ 371 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 372 #define CONFIG_HARD_I2C /* I2C with hardware support */ 373 #define CONFIG_I2C_MULTI_BUS 374 #define CONFIG_I2C_CMD_TREE 375 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 376 #define CONFIG_SYS_I2C_SLAVE 0x7F 377 #define CONFIG_SYS_I2C_OFFSET 0x118000 378 #define CONFIG_SYS_I2C2_OFFSET 0x118100 379 380 /* 381 * RapidIO 382 */ 383 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 384 #ifdef CONFIG_PHYS_64BIT 385 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 386 #else 387 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 388 #endif 389 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 390 391 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 392 #ifdef CONFIG_PHYS_64BIT 393 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 394 #else 395 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 396 #endif 397 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 398 399 /* 400 * for slave u-boot IMAGE instored in master memory space, 401 * PHYS must be aligned based on the SIZE 402 */ 403 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 404 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 405 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 406 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 407 /* 408 * for slave UCODE and ENV instored in master memory space, 409 * PHYS must be aligned based on the SIZE 410 */ 411 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 412 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 413 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 414 415 /* slave core release by master*/ 416 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 417 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 418 419 /* 420 * SRIO_PCIE_BOOT - SLAVE 421 */ 422 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 423 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 424 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 425 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 426 #endif 427 428 /* 429 * eSPI - Enhanced SPI 430 */ 431 #define CONFIG_FSL_ESPI 432 #define CONFIG_SPI_FLASH 433 #define CONFIG_SPI_FLASH_SPANSION 434 #define CONFIG_CMD_SF 435 #define CONFIG_SF_DEFAULT_SPEED 10000000 436 #define CONFIG_SF_DEFAULT_MODE 0 437 438 /* 439 * General PCI 440 * Memory space is mapped 1-1, but I/O space must start from 0. 441 */ 442 443 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 444 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 445 #ifdef CONFIG_PHYS_64BIT 446 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 447 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 448 #else 449 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 450 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 451 #endif 452 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 453 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 454 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 455 #ifdef CONFIG_PHYS_64BIT 456 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 457 #else 458 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 459 #endif 460 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 461 462 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 463 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 464 #ifdef CONFIG_PHYS_64BIT 465 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 466 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 467 #else 468 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 469 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 470 #endif 471 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 472 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 473 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 476 #else 477 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 478 #endif 479 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 480 481 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 482 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 483 #ifdef CONFIG_PHYS_64BIT 484 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 485 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 486 #else 487 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 488 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 489 #endif 490 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 491 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 492 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 493 #ifdef CONFIG_PHYS_64BIT 494 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 495 #else 496 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 497 #endif 498 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 499 500 /* controller 4, Base address 203000 */ 501 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 502 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 503 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 504 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 505 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 506 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 507 508 /* Qman/Bman */ 509 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 510 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 511 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 512 #ifdef CONFIG_PHYS_64BIT 513 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 514 #else 515 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 516 #endif 517 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 518 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 519 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 520 #ifdef CONFIG_PHYS_64BIT 521 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 522 #else 523 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 524 #endif 525 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 526 527 #define CONFIG_SYS_DPAA_FMAN 528 #define CONFIG_SYS_DPAA_PME 529 /* Default address of microcode for the Linux Fman driver */ 530 #if defined(CONFIG_SPIFLASH) 531 /* 532 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 533 * env, so we got 0x110000. 534 */ 535 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 536 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 537 #elif defined(CONFIG_SDCARD) 538 /* 539 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 540 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 541 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 542 */ 543 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 544 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 545 #elif defined(CONFIG_NAND) 546 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 547 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 548 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 549 /* 550 * Slave has no ucode locally, it can fetch this from remote. When implementing 551 * in two corenet boards, slave's ucode could be stored in master's memory 552 * space, the address can be mapped from slave TLB->slave LAW-> 553 * slave SRIO or PCIE outbound window->master inbound window-> 554 * master LAW->the ucode address in master's memory space. 555 */ 556 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 557 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 558 #else 559 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 560 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 561 #endif 562 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 563 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 564 565 #ifdef CONFIG_SYS_DPAA_FMAN 566 #define CONFIG_FMAN_ENET 567 #define CONFIG_PHYLIB_10G 568 #define CONFIG_PHY_VITESSE 569 #define CONFIG_PHY_TERANETICS 570 #endif 571 572 #ifdef CONFIG_PCI 573 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 574 #define CONFIG_E1000 575 576 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 577 #define CONFIG_DOS_PARTITION 578 #endif /* CONFIG_PCI */ 579 580 /* SATA */ 581 #ifdef CONFIG_FSL_SATA_V2 582 #define CONFIG_LIBATA 583 #define CONFIG_FSL_SATA 584 585 #define CONFIG_SYS_SATA_MAX_DEVICE 2 586 #define CONFIG_SATA1 587 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 588 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 589 #define CONFIG_SATA2 590 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 591 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 592 593 #define CONFIG_LBA48 594 #define CONFIG_CMD_SATA 595 #define CONFIG_DOS_PARTITION 596 #define CONFIG_CMD_EXT2 597 #endif 598 599 #ifdef CONFIG_FMAN_ENET 600 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 601 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 602 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 603 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 604 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 605 606 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 607 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 608 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 609 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 610 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 611 612 #define CONFIG_SYS_TBIPA_VALUE 8 613 #define CONFIG_MII /* MII PHY management */ 614 #define CONFIG_ETHPRIME "FM1@DTSEC1" 615 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 616 #endif 617 618 /* 619 * Environment 620 */ 621 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 622 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 623 624 /* 625 * Command line configuration. 626 */ 627 #include <config_cmd_default.h> 628 629 #define CONFIG_CMD_DHCP 630 #define CONFIG_CMD_ELF 631 #define CONFIG_CMD_ERRATA 632 #define CONFIG_CMD_GREPENV 633 #define CONFIG_CMD_IRQ 634 #define CONFIG_CMD_I2C 635 #define CONFIG_CMD_MII 636 #define CONFIG_CMD_PING 637 #define CONFIG_CMD_SETEXPR 638 #define CONFIG_CMD_REGINFO 639 640 #ifdef CONFIG_PCI 641 #define CONFIG_CMD_PCI 642 #define CONFIG_CMD_NET 643 #endif 644 645 /* 646 * USB 647 */ 648 #define CONFIG_HAS_FSL_DR_USB 649 #define CONFIG_HAS_FSL_MPH_USB 650 651 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 652 #define CONFIG_CMD_USB 653 #define CONFIG_USB_STORAGE 654 #define CONFIG_USB_EHCI 655 #define CONFIG_USB_EHCI_FSL 656 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 657 #define CONFIG_CMD_EXT2 658 #endif 659 660 #ifdef CONFIG_MMC 661 #define CONFIG_FSL_ESDHC 662 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 663 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 664 #define CONFIG_CMD_MMC 665 #define CONFIG_GENERIC_MMC 666 #define CONFIG_CMD_EXT2 667 #define CONFIG_CMD_FAT 668 #define CONFIG_DOS_PARTITION 669 #endif 670 671 /* 672 * Miscellaneous configurable options 673 */ 674 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 675 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 676 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 677 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 678 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 679 #ifdef CONFIG_CMD_KGDB 680 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 681 #else 682 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 683 #endif 684 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 685 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 686 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 687 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 688 689 /* 690 * For booting Linux, the board info and command line data 691 * have to be in the first 64 MB of memory, since this is 692 * the maximum mapped by the Linux kernel during initialization. 693 */ 694 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 695 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 696 697 #ifdef CONFIG_CMD_KGDB 698 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 699 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 700 #endif 701 702 /* 703 * Environment Configuration 704 */ 705 #define CONFIG_ROOTPATH "/opt/nfsroot" 706 #define CONFIG_BOOTFILE "uImage" 707 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 708 709 /* default location for tftp and bootm */ 710 #define CONFIG_LOADADDR 1000000 711 712 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 713 714 #define CONFIG_BAUDRATE 115200 715 716 #if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS) 717 #define __USB_PHY_TYPE ulpi 718 #else 719 #define __USB_PHY_TYPE utmi 720 #endif 721 722 #define CONFIG_EXTRA_ENV_SETTINGS \ 723 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 724 "bank_intlv=cs0_cs1;" \ 725 "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\ 726 "netdev=eth0\0" \ 727 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 728 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ 729 "tftpflash=tftpboot $loadaddr $uboot && " \ 730 "protect off $ubootaddr +$filesize && " \ 731 "erase $ubootaddr +$filesize && " \ 732 "cp.b $loadaddr $ubootaddr $filesize && " \ 733 "protect on $ubootaddr +$filesize && " \ 734 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 735 "consoledev=ttyS0\0" \ 736 "ramdiskaddr=2000000\0" \ 737 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 738 "fdtaddr=c00000\0" \ 739 "fdtfile=p4080ds/p4080ds.dtb\0" \ 740 "bdev=sda3\0" \ 741 "c=ffe\0" 742 743 #define CONFIG_HDBOOT \ 744 "setenv bootargs root=/dev/$bdev rw " \ 745 "console=$consoledev,$baudrate $othbootargs;" \ 746 "tftp $loadaddr $bootfile;" \ 747 "tftp $fdtaddr $fdtfile;" \ 748 "bootm $loadaddr - $fdtaddr" 749 750 #define CONFIG_NFSBOOTCOMMAND \ 751 "setenv bootargs root=/dev/nfs rw " \ 752 "nfsroot=$serverip:$rootpath " \ 753 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 754 "console=$consoledev,$baudrate $othbootargs;" \ 755 "tftp $loadaddr $bootfile;" \ 756 "tftp $fdtaddr $fdtfile;" \ 757 "bootm $loadaddr - $fdtaddr" 758 759 #define CONFIG_RAMBOOTCOMMAND \ 760 "setenv bootargs root=/dev/ram rw " \ 761 "console=$consoledev,$baudrate $othbootargs;" \ 762 "tftp $ramdiskaddr $ramdiskfile;" \ 763 "tftp $loadaddr $bootfile;" \ 764 "tftp $fdtaddr $fdtfile;" \ 765 "bootm $loadaddr $ramdiskaddr $fdtaddr" 766 767 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 768 769 #ifdef CONFIG_SECURE_BOOT 770 #include <asm/fsl_secure_boot.h> 771 #endif 772 773 #endif /* __CONFIG_H */ 774