1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_TARGET_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_TARGET_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_TARGET_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_TARGET_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #endif 46 47 /* High Level Configuration Options */ 48 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 49 #define CONFIG_MP /* support multiple processors */ 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xeff40000 53 #endif 54 55 #ifndef CONFIG_RESET_VECTOR_ADDRESS 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 57 #endif 58 59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 60 #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS 61 #define CONFIG_PCIE1 /* PCIE controller 1 */ 62 #define CONFIG_PCIE2 /* PCIE controller 2 */ 63 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 64 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 65 66 #define CONFIG_ENV_OVERWRITE 67 68 #ifndef CONFIG_MTD_NOR_FLASH 69 #else 70 #define CONFIG_FLASH_CFI_DRIVER 71 #define CONFIG_SYS_FLASH_CFI 72 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 73 #endif 74 75 #if defined(CONFIG_SPIFLASH) 76 #define CONFIG_SYS_EXTRA_ENV_RELOC 77 #define CONFIG_ENV_SPI_BUS 0 78 #define CONFIG_ENV_SPI_CS 0 79 #define CONFIG_ENV_SPI_MAX_HZ 10000000 80 #define CONFIG_ENV_SPI_MODE 0 81 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 82 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 83 #define CONFIG_ENV_SECT_SIZE 0x10000 84 #elif defined(CONFIG_SDCARD) 85 #define CONFIG_SYS_EXTRA_ENV_RELOC 86 #define CONFIG_FSL_FIXED_MMC_LOCATION 87 #define CONFIG_SYS_MMC_ENV_DEV 0 88 #define CONFIG_ENV_SIZE 0x2000 89 #define CONFIG_ENV_OFFSET (512 * 1658) 90 #elif defined(CONFIG_NAND) 91 #define CONFIG_SYS_EXTRA_ENV_RELOC 92 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 93 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 94 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 95 #define CONFIG_ENV_IS_IN_REMOTE 96 #define CONFIG_ENV_ADDR 0xffe20000 97 #define CONFIG_ENV_SIZE 0x2000 98 #elif defined(CONFIG_ENV_IS_NOWHERE) 99 #define CONFIG_ENV_SIZE 0x2000 100 #else 101 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 102 #define CONFIG_ENV_SIZE 0x2000 103 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 104 #endif 105 106 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 107 108 /* 109 * These can be toggled for performance analysis, otherwise use default. 110 */ 111 #define CONFIG_SYS_CACHE_STASHING 112 #define CONFIG_BACKSIDE_L2_CACHE 113 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 114 #define CONFIG_BTB /* toggle branch predition */ 115 #define CONFIG_DDR_ECC 116 #ifdef CONFIG_DDR_ECC 117 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 118 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 119 #endif 120 121 #define CONFIG_ENABLE_36BIT_PHYS 122 123 #ifdef CONFIG_PHYS_64BIT 124 #define CONFIG_ADDR_MAP 125 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 126 #endif 127 128 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 129 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 130 #define CONFIG_SYS_MEMTEST_END 0x00400000 131 #define CONFIG_SYS_ALT_MEMTEST 132 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 133 134 /* 135 * Config the L3 Cache as L3 SRAM 136 */ 137 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 138 #ifdef CONFIG_PHYS_64BIT 139 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 140 #else 141 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 142 #endif 143 #define CONFIG_SYS_L3_SIZE (1024 << 10) 144 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 145 146 #ifdef CONFIG_PHYS_64BIT 147 #define CONFIG_SYS_DCSRBAR 0xf0000000 148 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 149 #endif 150 151 /* EEPROM */ 152 #define CONFIG_ID_EEPROM 153 #define CONFIG_SYS_I2C_EEPROM_NXID 154 #define CONFIG_SYS_EEPROM_BUS_NUM 0 155 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 156 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 157 158 /* 159 * DDR Setup 160 */ 161 #define CONFIG_VERY_BIG_RAM 162 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 163 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 164 165 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 166 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 167 168 #define CONFIG_DDR_SPD 169 170 #define CONFIG_SYS_SPD_BUS_NUM 1 171 #define SPD_EEPROM_ADDRESS1 0x51 172 #define SPD_EEPROM_ADDRESS2 0x52 173 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 174 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 175 176 /* 177 * Local Bus Definitions 178 */ 179 180 /* Set the local bus clock 1/8 of platform clock */ 181 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 182 183 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 184 #ifdef CONFIG_PHYS_64BIT 185 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 186 #else 187 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 188 #endif 189 190 #define CONFIG_SYS_FLASH_BR_PRELIM \ 191 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 192 | BR_PS_16 | BR_V) 193 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 194 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 195 196 #define CONFIG_SYS_BR1_PRELIM \ 197 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 198 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 199 200 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 201 #ifdef CONFIG_PHYS_64BIT 202 #define PIXIS_BASE_PHYS 0xfffdf0000ull 203 #else 204 #define PIXIS_BASE_PHYS PIXIS_BASE 205 #endif 206 207 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 208 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 209 210 #define PIXIS_LBMAP_SWITCH 7 211 #define PIXIS_LBMAP_MASK 0xf0 212 #define PIXIS_LBMAP_SHIFT 4 213 #define PIXIS_LBMAP_ALTBANK 0x40 214 215 #define CONFIG_SYS_FLASH_QUIET_TEST 216 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 217 218 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 219 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 220 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 221 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 222 223 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 224 225 #if defined(CONFIG_RAMBOOT_PBL) 226 #define CONFIG_SYS_RAMBOOT 227 #endif 228 229 /* Nand Flash */ 230 #ifdef CONFIG_NAND_FSL_ELBC 231 #define CONFIG_SYS_NAND_BASE 0xffa00000 232 #ifdef CONFIG_PHYS_64BIT 233 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 234 #else 235 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 236 #endif 237 238 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 239 #define CONFIG_SYS_MAX_NAND_DEVICE 1 240 #define CONFIG_CMD_NAND 241 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 242 243 /* NAND flash config */ 244 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 245 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 246 | BR_PS_8 /* Port Size = 8 bit */ \ 247 | BR_MS_FCM /* MSEL = FCM */ \ 248 | BR_V) /* valid */ 249 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 250 | OR_FCM_PGS /* Large Page*/ \ 251 | OR_FCM_CSCT \ 252 | OR_FCM_CST \ 253 | OR_FCM_CHT \ 254 | OR_FCM_SCY_1 \ 255 | OR_FCM_TRLX \ 256 | OR_FCM_EHTR) 257 258 #ifdef CONFIG_NAND 259 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 260 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 261 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 262 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 263 #else 264 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 265 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 266 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 267 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 268 #endif 269 #else 270 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 271 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 272 #endif /* CONFIG_NAND_FSL_ELBC */ 273 274 #define CONFIG_SYS_FLASH_EMPTY_INFO 275 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 276 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 277 278 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 279 #define CONFIG_MISC_INIT_R 280 281 #define CONFIG_HWCONFIG 282 283 /* define to use L1 as initial stack */ 284 #define CONFIG_L1_INIT_RAM 285 #define CONFIG_SYS_INIT_RAM_LOCK 286 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 287 #ifdef CONFIG_PHYS_64BIT 288 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 289 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 290 /* The assembler doesn't like typecast */ 291 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 292 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 293 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 294 #else 295 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 296 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 297 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 298 #endif 299 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 300 301 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 302 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 303 304 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 305 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 306 307 /* Serial Port - controlled on board with jumper J8 308 * open - index 2 309 * shorted - index 1 310 */ 311 #define CONFIG_CONS_INDEX 1 312 #define CONFIG_SYS_NS16550_SERIAL 313 #define CONFIG_SYS_NS16550_REG_SIZE 1 314 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 315 316 #define CONFIG_SYS_BAUDRATE_TABLE \ 317 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 318 319 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 320 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 321 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 322 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 323 324 /* I2C */ 325 #define CONFIG_SYS_I2C 326 #define CONFIG_SYS_I2C_FSL 327 #define CONFIG_SYS_FSL_I2C_SPEED 400000 328 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 329 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 330 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 331 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 332 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 333 334 /* 335 * RapidIO 336 */ 337 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 338 #ifdef CONFIG_PHYS_64BIT 339 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 340 #else 341 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 342 #endif 343 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 344 345 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 346 #ifdef CONFIG_PHYS_64BIT 347 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 348 #else 349 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 350 #endif 351 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 352 353 /* 354 * for slave u-boot IMAGE instored in master memory space, 355 * PHYS must be aligned based on the SIZE 356 */ 357 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 358 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 359 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 360 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 361 /* 362 * for slave UCODE and ENV instored in master memory space, 363 * PHYS must be aligned based on the SIZE 364 */ 365 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 366 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 367 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 368 369 /* slave core release by master*/ 370 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 371 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 372 373 /* 374 * SRIO_PCIE_BOOT - SLAVE 375 */ 376 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 377 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 378 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 379 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 380 #endif 381 382 /* 383 * eSPI - Enhanced SPI 384 */ 385 #define CONFIG_SF_DEFAULT_SPEED 10000000 386 #define CONFIG_SF_DEFAULT_MODE 0 387 388 /* 389 * General PCI 390 * Memory space is mapped 1-1, but I/O space must start from 0. 391 */ 392 393 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 394 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 395 #ifdef CONFIG_PHYS_64BIT 396 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 397 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 398 #else 399 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 400 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 401 #endif 402 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 403 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 404 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 405 #ifdef CONFIG_PHYS_64BIT 406 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 407 #else 408 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 409 #endif 410 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 411 412 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 413 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 414 #ifdef CONFIG_PHYS_64BIT 415 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 416 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 417 #else 418 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 419 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 420 #endif 421 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 422 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 423 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 424 #ifdef CONFIG_PHYS_64BIT 425 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 426 #else 427 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 428 #endif 429 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 430 431 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 432 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 433 #ifdef CONFIG_PHYS_64BIT 434 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 435 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 436 #else 437 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 438 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 439 #endif 440 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 441 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 442 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 443 #ifdef CONFIG_PHYS_64BIT 444 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 445 #else 446 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 447 #endif 448 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 449 450 /* controller 4, Base address 203000 */ 451 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 452 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 453 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 454 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 455 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 456 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 457 458 /* Qman/Bman */ 459 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 460 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 461 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 462 #ifdef CONFIG_PHYS_64BIT 463 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 464 #else 465 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 466 #endif 467 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 468 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 469 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 470 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 471 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 472 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 473 CONFIG_SYS_BMAN_CENA_SIZE) 474 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 475 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 476 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 477 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 478 #ifdef CONFIG_PHYS_64BIT 479 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 480 #else 481 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 482 #endif 483 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 484 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 485 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 486 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 487 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 488 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 489 CONFIG_SYS_QMAN_CENA_SIZE) 490 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 491 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 492 493 #define CONFIG_SYS_DPAA_FMAN 494 #define CONFIG_SYS_DPAA_PME 495 /* Default address of microcode for the Linux Fman driver */ 496 #if defined(CONFIG_SPIFLASH) 497 /* 498 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 499 * env, so we got 0x110000. 500 */ 501 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 502 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 503 #elif defined(CONFIG_SDCARD) 504 /* 505 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 506 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 507 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 508 */ 509 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 510 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 511 #elif defined(CONFIG_NAND) 512 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 513 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 514 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 515 /* 516 * Slave has no ucode locally, it can fetch this from remote. When implementing 517 * in two corenet boards, slave's ucode could be stored in master's memory 518 * space, the address can be mapped from slave TLB->slave LAW-> 519 * slave SRIO or PCIE outbound window->master inbound window-> 520 * master LAW->the ucode address in master's memory space. 521 */ 522 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 523 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 524 #else 525 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 526 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 527 #endif 528 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 529 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 530 531 #ifdef CONFIG_SYS_DPAA_FMAN 532 #define CONFIG_FMAN_ENET 533 #define CONFIG_PHYLIB_10G 534 #define CONFIG_PHY_VITESSE 535 #define CONFIG_PHY_TERANETICS 536 #endif 537 538 #ifdef CONFIG_PCI 539 #define CONFIG_PCI_INDIRECT_BRIDGE 540 541 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 542 #endif /* CONFIG_PCI */ 543 544 /* SATA */ 545 #ifdef CONFIG_FSL_SATA_V2 546 #define CONFIG_LIBATA 547 #define CONFIG_FSL_SATA 548 549 #define CONFIG_SYS_SATA_MAX_DEVICE 2 550 #define CONFIG_SATA1 551 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 552 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 553 #define CONFIG_SATA2 554 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 555 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 556 557 #define CONFIG_LBA48 558 #endif 559 560 #ifdef CONFIG_FMAN_ENET 561 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 562 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 563 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 564 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 565 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 566 567 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 568 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 569 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 570 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 571 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 572 573 #define CONFIG_SYS_TBIPA_VALUE 8 574 #define CONFIG_MII /* MII PHY management */ 575 #define CONFIG_ETHPRIME "FM1@DTSEC1" 576 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 577 #endif 578 579 /* 580 * Environment 581 */ 582 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 583 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 584 585 /* 586 * Command line configuration. 587 */ 588 #define CONFIG_CMD_REGINFO 589 590 #ifdef CONFIG_PCI 591 #define CONFIG_CMD_PCI 592 #endif 593 594 /* 595 * USB 596 */ 597 #define CONFIG_HAS_FSL_DR_USB 598 #define CONFIG_HAS_FSL_MPH_USB 599 600 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 601 #define CONFIG_USB_EHCI_FSL 602 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 603 #endif 604 605 #ifdef CONFIG_MMC 606 #define CONFIG_FSL_ESDHC 607 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 608 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 609 #endif 610 611 /* 612 * Miscellaneous configurable options 613 */ 614 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 615 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 616 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 617 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 618 #ifdef CONFIG_CMD_KGDB 619 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 620 #else 621 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 622 #endif 623 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 624 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 625 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 626 627 /* 628 * For booting Linux, the board info and command line data 629 * have to be in the first 64 MB of memory, since this is 630 * the maximum mapped by the Linux kernel during initialization. 631 */ 632 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 633 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 634 635 #ifdef CONFIG_CMD_KGDB 636 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 637 #endif 638 639 /* 640 * Environment Configuration 641 */ 642 #define CONFIG_ROOTPATH "/opt/nfsroot" 643 #define CONFIG_BOOTFILE "uImage" 644 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 645 646 /* default location for tftp and bootm */ 647 #define CONFIG_LOADADDR 1000000 648 649 #ifdef CONFIG_TARGET_P4080DS 650 #define __USB_PHY_TYPE ulpi 651 #else 652 #define __USB_PHY_TYPE utmi 653 #endif 654 655 #define CONFIG_EXTRA_ENV_SETTINGS \ 656 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 657 "bank_intlv=cs0_cs1;" \ 658 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 659 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 660 "netdev=eth0\0" \ 661 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 662 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 663 "tftpflash=tftpboot $loadaddr $uboot && " \ 664 "protect off $ubootaddr +$filesize && " \ 665 "erase $ubootaddr +$filesize && " \ 666 "cp.b $loadaddr $ubootaddr $filesize && " \ 667 "protect on $ubootaddr +$filesize && " \ 668 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 669 "consoledev=ttyS0\0" \ 670 "ramdiskaddr=2000000\0" \ 671 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 672 "fdtaddr=1e00000\0" \ 673 "fdtfile=p4080ds/p4080ds.dtb\0" \ 674 "bdev=sda3\0" 675 676 #define CONFIG_HDBOOT \ 677 "setenv bootargs root=/dev/$bdev rw " \ 678 "console=$consoledev,$baudrate $othbootargs;" \ 679 "tftp $loadaddr $bootfile;" \ 680 "tftp $fdtaddr $fdtfile;" \ 681 "bootm $loadaddr - $fdtaddr" 682 683 #define CONFIG_NFSBOOTCOMMAND \ 684 "setenv bootargs root=/dev/nfs rw " \ 685 "nfsroot=$serverip:$rootpath " \ 686 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 687 "console=$consoledev,$baudrate $othbootargs;" \ 688 "tftp $loadaddr $bootfile;" \ 689 "tftp $fdtaddr $fdtfile;" \ 690 "bootm $loadaddr - $fdtaddr" 691 692 #define CONFIG_RAMBOOTCOMMAND \ 693 "setenv bootargs root=/dev/ram rw " \ 694 "console=$consoledev,$baudrate $othbootargs;" \ 695 "tftp $ramdiskaddr $ramdiskfile;" \ 696 "tftp $loadaddr $bootfile;" \ 697 "tftp $fdtaddr $fdtfile;" \ 698 "bootm $loadaddr $ramdiskaddr $fdtaddr" 699 700 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 701 702 #include <asm/fsl_secure_boot.h> 703 704 #endif /* __CONFIG_H */ 705