1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 17 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 18 #define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/corenet_ds/pbi.cfg 19 #if defined(CONFIG_P3041DS) 20 #define CONFIG_SYS_FSL_PBL_RCW \ 21 $(SRCTREE)/board/freescale/corenet_ds/rcw_p3041ds.cfg 22 #elif defined(CONFIG_P4080DS) 23 #define CONFIG_SYS_FSL_PBL_RCW \ 24 $(SRCTREE)/board/freescale/corenet_ds/rcw_p4080ds.cfg 25 #elif defined(CONFIG_P5020DS) 26 #define CONFIG_SYS_FSL_PBL_RCW \ 27 $(SRCTREE)/board/freescale/corenet_ds/rcw_p5020ds.cfg 28 #elif defined(CONFIG_P5040DS) 29 #define CONFIG_SYS_FSL_PBL_RCW \ 30 $(SRCTREE)/board/freescale/corenet_ds/rcw_p5040ds.cfg 31 #endif 32 #endif 33 34 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 35 /* Set 1M boot space */ 36 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 37 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 38 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 39 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 40 #define CONFIG_SYS_NO_FLASH 41 #endif 42 43 /* High Level Configuration Options */ 44 #define CONFIG_BOOKE 45 #define CONFIG_E500 /* BOOKE e500 family */ 46 #define CONFIG_E500MC /* BOOKE e500mc family */ 47 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 48 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 49 #define CONFIG_MP /* support multiple processors */ 50 51 #ifndef CONFIG_SYS_TEXT_BASE 52 #define CONFIG_SYS_TEXT_BASE 0xeff40000 53 #endif 54 55 #ifndef CONFIG_RESET_VECTOR_ADDRESS 56 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 57 #endif 58 59 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 60 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 61 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 62 #define CONFIG_PCI /* Enable PCI/PCIE */ 63 #define CONFIG_PCIE1 /* PCIE controler 1 */ 64 #define CONFIG_PCIE2 /* PCIE controler 2 */ 65 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 66 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 67 68 #define CONFIG_FSL_LAW /* Use common FSL init code */ 69 70 #define CONFIG_ENV_OVERWRITE 71 72 #ifdef CONFIG_SYS_NO_FLASH 73 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 74 #define CONFIG_ENV_IS_NOWHERE 75 #endif 76 #else 77 #define CONFIG_FLASH_CFI_DRIVER 78 #define CONFIG_SYS_FLASH_CFI 79 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 80 #endif 81 82 #if defined(CONFIG_SPIFLASH) 83 #define CONFIG_SYS_EXTRA_ENV_RELOC 84 #define CONFIG_ENV_IS_IN_SPI_FLASH 85 #define CONFIG_ENV_SPI_BUS 0 86 #define CONFIG_ENV_SPI_CS 0 87 #define CONFIG_ENV_SPI_MAX_HZ 10000000 88 #define CONFIG_ENV_SPI_MODE 0 89 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 90 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 91 #define CONFIG_ENV_SECT_SIZE 0x10000 92 #elif defined(CONFIG_SDCARD) 93 #define CONFIG_SYS_EXTRA_ENV_RELOC 94 #define CONFIG_ENV_IS_IN_MMC 95 #define CONFIG_FSL_FIXED_MMC_LOCATION 96 #define CONFIG_SYS_MMC_ENV_DEV 0 97 #define CONFIG_ENV_SIZE 0x2000 98 #define CONFIG_ENV_OFFSET (512 * 1658) 99 #elif defined(CONFIG_NAND) 100 #define CONFIG_SYS_EXTRA_ENV_RELOC 101 #define CONFIG_ENV_IS_IN_NAND 102 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 103 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 104 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 105 #define CONFIG_ENV_IS_IN_REMOTE 106 #define CONFIG_ENV_ADDR 0xffe20000 107 #define CONFIG_ENV_SIZE 0x2000 108 #elif defined(CONFIG_ENV_IS_NOWHERE) 109 #define CONFIG_ENV_SIZE 0x2000 110 #else 111 #define CONFIG_ENV_IS_IN_FLASH 112 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 113 #define CONFIG_ENV_SIZE 0x2000 114 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 115 #endif 116 117 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 118 119 /* 120 * These can be toggled for performance analysis, otherwise use default. 121 */ 122 #define CONFIG_SYS_CACHE_STASHING 123 #define CONFIG_BACKSIDE_L2_CACHE 124 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 125 #define CONFIG_BTB /* toggle branch predition */ 126 #define CONFIG_DDR_ECC 127 #ifdef CONFIG_DDR_ECC 128 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 129 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 130 #endif 131 132 #define CONFIG_ENABLE_36BIT_PHYS 133 134 #ifdef CONFIG_PHYS_64BIT 135 #define CONFIG_ADDR_MAP 136 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 137 #endif 138 139 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 140 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 141 #define CONFIG_SYS_MEMTEST_END 0x00400000 142 #define CONFIG_SYS_ALT_MEMTEST 143 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 144 145 /* 146 * Config the L3 Cache as L3 SRAM 147 */ 148 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 149 #ifdef CONFIG_PHYS_64BIT 150 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 151 #else 152 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 153 #endif 154 #define CONFIG_SYS_L3_SIZE (1024 << 10) 155 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 156 157 #ifdef CONFIG_PHYS_64BIT 158 #define CONFIG_SYS_DCSRBAR 0xf0000000 159 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 160 #endif 161 162 /* EEPROM */ 163 #define CONFIG_ID_EEPROM 164 #define CONFIG_SYS_I2C_EEPROM_NXID 165 #define CONFIG_SYS_EEPROM_BUS_NUM 0 166 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 167 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 168 169 /* 170 * DDR Setup 171 */ 172 #define CONFIG_VERY_BIG_RAM 173 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 174 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 175 176 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 177 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 178 179 #define CONFIG_DDR_SPD 180 #define CONFIG_SYS_FSL_DDR3 181 182 #define CONFIG_SYS_SPD_BUS_NUM 1 183 #define SPD_EEPROM_ADDRESS1 0x51 184 #define SPD_EEPROM_ADDRESS2 0x52 185 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 186 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 187 188 /* 189 * Local Bus Definitions 190 */ 191 192 /* Set the local bus clock 1/8 of platform clock */ 193 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 194 195 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 196 #ifdef CONFIG_PHYS_64BIT 197 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 198 #else 199 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 200 #endif 201 202 #define CONFIG_SYS_FLASH_BR_PRELIM \ 203 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 204 | BR_PS_16 | BR_V) 205 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 206 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 207 208 #define CONFIG_SYS_BR1_PRELIM \ 209 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 210 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 211 212 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 213 #ifdef CONFIG_PHYS_64BIT 214 #define PIXIS_BASE_PHYS 0xfffdf0000ull 215 #else 216 #define PIXIS_BASE_PHYS PIXIS_BASE 217 #endif 218 219 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 220 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 221 222 #define PIXIS_LBMAP_SWITCH 7 223 #define PIXIS_LBMAP_MASK 0xf0 224 #define PIXIS_LBMAP_SHIFT 4 225 #define PIXIS_LBMAP_ALTBANK 0x40 226 227 #define CONFIG_SYS_FLASH_QUIET_TEST 228 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 229 230 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 231 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 232 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 233 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 234 235 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 236 237 #if defined(CONFIG_RAMBOOT_PBL) 238 #define CONFIG_SYS_RAMBOOT 239 #endif 240 241 /* Nand Flash */ 242 #ifdef CONFIG_NAND_FSL_ELBC 243 #define CONFIG_SYS_NAND_BASE 0xffa00000 244 #ifdef CONFIG_PHYS_64BIT 245 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 246 #else 247 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 248 #endif 249 250 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 251 #define CONFIG_SYS_MAX_NAND_DEVICE 1 252 #define CONFIG_MTD_NAND_VERIFY_WRITE 253 #define CONFIG_CMD_NAND 254 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 255 256 /* NAND flash config */ 257 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 258 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 259 | BR_PS_8 /* Port Size = 8 bit */ \ 260 | BR_MS_FCM /* MSEL = FCM */ \ 261 | BR_V) /* valid */ 262 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 263 | OR_FCM_PGS /* Large Page*/ \ 264 | OR_FCM_CSCT \ 265 | OR_FCM_CST \ 266 | OR_FCM_CHT \ 267 | OR_FCM_SCY_1 \ 268 | OR_FCM_TRLX \ 269 | OR_FCM_EHTR) 270 271 #ifdef CONFIG_NAND 272 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 273 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 274 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 275 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 276 #else 277 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 278 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 279 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 280 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 281 #endif 282 #else 283 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 284 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 285 #endif /* CONFIG_NAND_FSL_ELBC */ 286 287 #define CONFIG_SYS_FLASH_EMPTY_INFO 288 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 289 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 290 291 #define CONFIG_BOARD_EARLY_INIT_F 292 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 293 #define CONFIG_MISC_INIT_R 294 295 #define CONFIG_HWCONFIG 296 297 /* define to use L1 as initial stack */ 298 #define CONFIG_L1_INIT_RAM 299 #define CONFIG_SYS_INIT_RAM_LOCK 300 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 301 #ifdef CONFIG_PHYS_64BIT 302 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 304 /* The assembler doesn't like typecast */ 305 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 306 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 307 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 308 #else 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 311 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 312 #endif 313 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 314 315 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 316 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 317 318 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 319 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 320 321 /* Serial Port - controlled on board with jumper J8 322 * open - index 2 323 * shorted - index 1 324 */ 325 #define CONFIG_CONS_INDEX 1 326 #define CONFIG_SYS_NS16550 327 #define CONFIG_SYS_NS16550_SERIAL 328 #define CONFIG_SYS_NS16550_REG_SIZE 1 329 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 330 331 #define CONFIG_SYS_BAUDRATE_TABLE \ 332 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 333 334 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 335 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 336 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 337 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 338 339 /* Use the HUSH parser */ 340 #define CONFIG_SYS_HUSH_PARSER 341 342 /* pass open firmware flat tree */ 343 #define CONFIG_OF_LIBFDT 344 #define CONFIG_OF_BOARD_SETUP 345 #define CONFIG_OF_STDOUT_VIA_ALIAS 346 347 /* new uImage format support */ 348 #define CONFIG_FIT 349 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 350 351 /* I2C */ 352 #define CONFIG_SYS_I2C 353 #define CONFIG_SYS_I2C_FSL 354 #define CONFIG_SYS_FSL_I2C_SPEED 400000 355 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 356 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 357 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 358 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 359 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 360 361 /* 362 * RapidIO 363 */ 364 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 365 #ifdef CONFIG_PHYS_64BIT 366 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 367 #else 368 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 369 #endif 370 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 371 372 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 373 #ifdef CONFIG_PHYS_64BIT 374 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 375 #else 376 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 377 #endif 378 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 379 380 /* 381 * for slave u-boot IMAGE instored in master memory space, 382 * PHYS must be aligned based on the SIZE 383 */ 384 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull 385 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull 386 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000 /* 512K */ 387 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull 388 /* 389 * for slave UCODE and ENV instored in master memory space, 390 * PHYS must be aligned based on the SIZE 391 */ 392 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull 393 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 394 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 395 396 /* slave core release by master*/ 397 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 398 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 399 400 /* 401 * SRIO_PCIE_BOOT - SLAVE 402 */ 403 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 404 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 405 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 406 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 407 #endif 408 409 /* 410 * eSPI - Enhanced SPI 411 */ 412 #define CONFIG_FSL_ESPI 413 #define CONFIG_SPI_FLASH 414 #define CONFIG_SPI_FLASH_SPANSION 415 #define CONFIG_CMD_SF 416 #define CONFIG_SF_DEFAULT_SPEED 10000000 417 #define CONFIG_SF_DEFAULT_MODE 0 418 419 /* 420 * General PCI 421 * Memory space is mapped 1-1, but I/O space must start from 0. 422 */ 423 424 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 425 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 428 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 429 #else 430 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 431 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 432 #endif 433 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 434 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 435 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 436 #ifdef CONFIG_PHYS_64BIT 437 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 438 #else 439 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 440 #endif 441 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 442 443 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 444 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 445 #ifdef CONFIG_PHYS_64BIT 446 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 447 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 448 #else 449 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 450 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 451 #endif 452 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 453 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 454 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 455 #ifdef CONFIG_PHYS_64BIT 456 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 457 #else 458 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 459 #endif 460 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 461 462 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 463 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 464 #ifdef CONFIG_PHYS_64BIT 465 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 466 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 467 #else 468 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 469 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 470 #endif 471 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 472 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 473 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 476 #else 477 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 478 #endif 479 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 480 481 /* controller 4, Base address 203000 */ 482 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 483 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 484 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 485 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 486 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 487 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 488 489 /* Qman/Bman */ 490 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 491 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 492 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 493 #ifdef CONFIG_PHYS_64BIT 494 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 495 #else 496 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 497 #endif 498 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 499 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 500 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 501 #ifdef CONFIG_PHYS_64BIT 502 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 503 #else 504 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 505 #endif 506 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 507 508 #define CONFIG_SYS_DPAA_FMAN 509 #define CONFIG_SYS_DPAA_PME 510 /* Default address of microcode for the Linux Fman driver */ 511 #if defined(CONFIG_SPIFLASH) 512 /* 513 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 514 * env, so we got 0x110000. 515 */ 516 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 517 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 518 #elif defined(CONFIG_SDCARD) 519 /* 520 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 521 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 522 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 523 */ 524 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 525 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1680) 526 #elif defined(CONFIG_NAND) 527 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 528 #define CONFIG_SYS_QE_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 529 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 530 /* 531 * Slave has no ucode locally, it can fetch this from remote. When implementing 532 * in two corenet boards, slave's ucode could be stored in master's memory 533 * space, the address can be mapped from slave TLB->slave LAW-> 534 * slave SRIO or PCIE outbound window->master inbound window-> 535 * master LAW->the ucode address in master's memory space. 536 */ 537 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 538 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 539 #else 540 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 541 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEFF00000 542 #endif 543 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 544 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 545 546 #ifdef CONFIG_SYS_DPAA_FMAN 547 #define CONFIG_FMAN_ENET 548 #define CONFIG_PHYLIB_10G 549 #define CONFIG_PHY_VITESSE 550 #define CONFIG_PHY_TERANETICS 551 #endif 552 553 #ifdef CONFIG_PCI 554 #define CONFIG_PCI_INDIRECT_BRIDGE 555 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 556 #define CONFIG_E1000 557 558 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 559 #define CONFIG_DOS_PARTITION 560 #endif /* CONFIG_PCI */ 561 562 /* SATA */ 563 #ifdef CONFIG_FSL_SATA_V2 564 #define CONFIG_LIBATA 565 #define CONFIG_FSL_SATA 566 567 #define CONFIG_SYS_SATA_MAX_DEVICE 2 568 #define CONFIG_SATA1 569 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 570 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 571 #define CONFIG_SATA2 572 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 573 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 574 575 #define CONFIG_LBA48 576 #define CONFIG_CMD_SATA 577 #define CONFIG_DOS_PARTITION 578 #define CONFIG_CMD_EXT2 579 #endif 580 581 #ifdef CONFIG_FMAN_ENET 582 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 583 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 584 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 585 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 586 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 587 588 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 589 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 590 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 591 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 592 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 593 594 #define CONFIG_SYS_TBIPA_VALUE 8 595 #define CONFIG_MII /* MII PHY management */ 596 #define CONFIG_ETHPRIME "FM1@DTSEC1" 597 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 598 #endif 599 600 /* 601 * Environment 602 */ 603 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 604 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 605 606 /* 607 * Command line configuration. 608 */ 609 #include <config_cmd_default.h> 610 611 #define CONFIG_CMD_DHCP 612 #define CONFIG_CMD_ELF 613 #define CONFIG_CMD_ERRATA 614 #define CONFIG_CMD_GREPENV 615 #define CONFIG_CMD_IRQ 616 #define CONFIG_CMD_I2C 617 #define CONFIG_CMD_MII 618 #define CONFIG_CMD_PING 619 #define CONFIG_CMD_SETEXPR 620 #define CONFIG_CMD_REGINFO 621 622 #ifdef CONFIG_PCI 623 #define CONFIG_CMD_PCI 624 #define CONFIG_CMD_NET 625 #endif 626 627 /* 628 * USB 629 */ 630 #define CONFIG_HAS_FSL_DR_USB 631 #define CONFIG_HAS_FSL_MPH_USB 632 633 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 634 #define CONFIG_CMD_USB 635 #define CONFIG_USB_STORAGE 636 #define CONFIG_USB_EHCI 637 #define CONFIG_USB_EHCI_FSL 638 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 639 #define CONFIG_CMD_EXT2 640 #endif 641 642 #ifdef CONFIG_MMC 643 #define CONFIG_FSL_ESDHC 644 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 645 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 646 #define CONFIG_CMD_MMC 647 #define CONFIG_GENERIC_MMC 648 #define CONFIG_CMD_EXT2 649 #define CONFIG_CMD_FAT 650 #define CONFIG_DOS_PARTITION 651 #endif 652 653 /* 654 * Miscellaneous configurable options 655 */ 656 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 657 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 658 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 659 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 660 #ifdef CONFIG_CMD_KGDB 661 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 662 #else 663 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 664 #endif 665 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 666 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 667 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 668 669 /* 670 * For booting Linux, the board info and command line data 671 * have to be in the first 64 MB of memory, since this is 672 * the maximum mapped by the Linux kernel during initialization. 673 */ 674 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 675 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 676 677 #ifdef CONFIG_CMD_KGDB 678 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 679 #endif 680 681 /* 682 * Environment Configuration 683 */ 684 #define CONFIG_ROOTPATH "/opt/nfsroot" 685 #define CONFIG_BOOTFILE "uImage" 686 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 687 688 /* default location for tftp and bootm */ 689 #define CONFIG_LOADADDR 1000000 690 691 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 692 693 #define CONFIG_BAUDRATE 115200 694 695 #ifdef CONFIG_P4080DS 696 #define __USB_PHY_TYPE ulpi 697 #else 698 #define __USB_PHY_TYPE utmi 699 #endif 700 701 #define CONFIG_EXTRA_ENV_SETTINGS \ 702 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 703 "bank_intlv=cs0_cs1;" \ 704 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 705 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 706 "netdev=eth0\0" \ 707 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 708 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 709 "tftpflash=tftpboot $loadaddr $uboot && " \ 710 "protect off $ubootaddr +$filesize && " \ 711 "erase $ubootaddr +$filesize && " \ 712 "cp.b $loadaddr $ubootaddr $filesize && " \ 713 "protect on $ubootaddr +$filesize && " \ 714 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 715 "consoledev=ttyS0\0" \ 716 "ramdiskaddr=2000000\0" \ 717 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 718 "fdtaddr=c00000\0" \ 719 "fdtfile=p4080ds/p4080ds.dtb\0" \ 720 "bdev=sda3\0" \ 721 "c=ffe\0" 722 723 #define CONFIG_HDBOOT \ 724 "setenv bootargs root=/dev/$bdev rw " \ 725 "console=$consoledev,$baudrate $othbootargs;" \ 726 "tftp $loadaddr $bootfile;" \ 727 "tftp $fdtaddr $fdtfile;" \ 728 "bootm $loadaddr - $fdtaddr" 729 730 #define CONFIG_NFSBOOTCOMMAND \ 731 "setenv bootargs root=/dev/nfs rw " \ 732 "nfsroot=$serverip:$rootpath " \ 733 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 734 "console=$consoledev,$baudrate $othbootargs;" \ 735 "tftp $loadaddr $bootfile;" \ 736 "tftp $fdtaddr $fdtfile;" \ 737 "bootm $loadaddr - $fdtaddr" 738 739 #define CONFIG_RAMBOOTCOMMAND \ 740 "setenv bootargs root=/dev/ram rw " \ 741 "console=$consoledev,$baudrate $othbootargs;" \ 742 "tftp $ramdiskaddr $ramdiskfile;" \ 743 "tftp $loadaddr $bootfile;" \ 744 "tftp $fdtaddr $fdtfile;" \ 745 "bootm $loadaddr $ramdiskaddr $fdtaddr" 746 747 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 748 749 #include <asm/fsl_secure_boot.h> 750 751 #endif /* __CONFIG_H */ 752