1 /* 2 * Copyright 2009-2012 Freescale Semiconductor, Inc. 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 /* 8 * Corenet DS style board configuration file 9 */ 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #include "../board/freescale/common/ics307_clk.h" 14 15 #ifdef CONFIG_RAMBOOT_PBL 16 #ifdef CONFIG_SECURE_BOOT 17 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 18 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 19 #ifdef CONFIG_NAND 20 #define CONFIG_RAMBOOT_NAND 21 #endif 22 #define CONFIG_BOOTSCRIPT_COPY_RAM 23 #else 24 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 25 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 26 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg 27 #if defined(CONFIG_TARGET_P3041DS) 28 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p3041ds.cfg 29 #elif defined(CONFIG_TARGET_P4080DS) 30 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p4080ds.cfg 31 #elif defined(CONFIG_TARGET_P5020DS) 32 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5020ds.cfg 33 #elif defined(CONFIG_TARGET_P5040DS) 34 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p5040ds.cfg 35 #endif 36 #endif 37 #endif 38 39 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 40 /* Set 1M boot space */ 41 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 42 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ 43 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) 44 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 45 #define CONFIG_SYS_NO_FLASH 46 #endif 47 48 /* High Level Configuration Options */ 49 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 50 #define CONFIG_MP /* support multiple processors */ 51 52 #ifndef CONFIG_SYS_TEXT_BASE 53 #define CONFIG_SYS_TEXT_BASE 0xeff40000 54 #endif 55 56 #ifndef CONFIG_RESET_VECTOR_ADDRESS 57 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 58 #endif 59 60 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 61 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 62 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 63 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ 64 #define CONFIG_PCIE1 /* PCIE controller 1 */ 65 #define CONFIG_PCIE2 /* PCIE controller 2 */ 66 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 67 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 68 69 #define CONFIG_ENV_OVERWRITE 70 71 #ifdef CONFIG_SYS_NO_FLASH 72 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL) 73 #define CONFIG_ENV_IS_NOWHERE 74 #endif 75 #else 76 #define CONFIG_FLASH_CFI_DRIVER 77 #define CONFIG_SYS_FLASH_CFI 78 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 79 #endif 80 81 #if defined(CONFIG_SPIFLASH) 82 #define CONFIG_SYS_EXTRA_ENV_RELOC 83 #define CONFIG_ENV_IS_IN_SPI_FLASH 84 #define CONFIG_ENV_SPI_BUS 0 85 #define CONFIG_ENV_SPI_CS 0 86 #define CONFIG_ENV_SPI_MAX_HZ 10000000 87 #define CONFIG_ENV_SPI_MODE 0 88 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 89 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 90 #define CONFIG_ENV_SECT_SIZE 0x10000 91 #elif defined(CONFIG_SDCARD) 92 #define CONFIG_SYS_EXTRA_ENV_RELOC 93 #define CONFIG_ENV_IS_IN_MMC 94 #define CONFIG_FSL_FIXED_MMC_LOCATION 95 #define CONFIG_SYS_MMC_ENV_DEV 0 96 #define CONFIG_ENV_SIZE 0x2000 97 #define CONFIG_ENV_OFFSET (512 * 1658) 98 #elif defined(CONFIG_NAND) 99 #define CONFIG_SYS_EXTRA_ENV_RELOC 100 #define CONFIG_ENV_IS_IN_NAND 101 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 102 #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) 103 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 104 #define CONFIG_ENV_IS_IN_REMOTE 105 #define CONFIG_ENV_ADDR 0xffe20000 106 #define CONFIG_ENV_SIZE 0x2000 107 #elif defined(CONFIG_ENV_IS_NOWHERE) 108 #define CONFIG_ENV_SIZE 0x2000 109 #else 110 #define CONFIG_ENV_IS_IN_FLASH 111 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 112 #define CONFIG_ENV_SIZE 0x2000 113 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 114 #endif 115 116 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 117 118 /* 119 * These can be toggled for performance analysis, otherwise use default. 120 */ 121 #define CONFIG_SYS_CACHE_STASHING 122 #define CONFIG_BACKSIDE_L2_CACHE 123 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 124 #define CONFIG_BTB /* toggle branch predition */ 125 #define CONFIG_DDR_ECC 126 #ifdef CONFIG_DDR_ECC 127 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 128 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 129 #endif 130 131 #define CONFIG_ENABLE_36BIT_PHYS 132 133 #ifdef CONFIG_PHYS_64BIT 134 #define CONFIG_ADDR_MAP 135 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 136 #endif 137 138 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 139 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 140 #define CONFIG_SYS_MEMTEST_END 0x00400000 141 #define CONFIG_SYS_ALT_MEMTEST 142 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 143 144 /* 145 * Config the L3 Cache as L3 SRAM 146 */ 147 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 148 #ifdef CONFIG_PHYS_64BIT 149 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 150 #else 151 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 152 #endif 153 #define CONFIG_SYS_L3_SIZE (1024 << 10) 154 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 155 156 #ifdef CONFIG_PHYS_64BIT 157 #define CONFIG_SYS_DCSRBAR 0xf0000000 158 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 159 #endif 160 161 /* EEPROM */ 162 #define CONFIG_ID_EEPROM 163 #define CONFIG_SYS_I2C_EEPROM_NXID 164 #define CONFIG_SYS_EEPROM_BUS_NUM 0 165 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 166 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 167 168 /* 169 * DDR Setup 170 */ 171 #define CONFIG_VERY_BIG_RAM 172 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 173 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 174 175 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 176 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 177 178 #define CONFIG_DDR_SPD 179 #define CONFIG_SYS_FSL_DDR3 180 181 #define CONFIG_SYS_SPD_BUS_NUM 1 182 #define SPD_EEPROM_ADDRESS1 0x51 183 #define SPD_EEPROM_ADDRESS2 0x52 184 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 185 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 186 187 /* 188 * Local Bus Definitions 189 */ 190 191 /* Set the local bus clock 1/8 of platform clock */ 192 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 193 194 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 195 #ifdef CONFIG_PHYS_64BIT 196 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 197 #else 198 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 199 #endif 200 201 #define CONFIG_SYS_FLASH_BR_PRELIM \ 202 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \ 203 | BR_PS_16 | BR_V) 204 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 205 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 206 207 #define CONFIG_SYS_BR1_PRELIM \ 208 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 209 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 210 211 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 212 #ifdef CONFIG_PHYS_64BIT 213 #define PIXIS_BASE_PHYS 0xfffdf0000ull 214 #else 215 #define PIXIS_BASE_PHYS PIXIS_BASE 216 #endif 217 218 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 219 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 220 221 #define PIXIS_LBMAP_SWITCH 7 222 #define PIXIS_LBMAP_MASK 0xf0 223 #define PIXIS_LBMAP_SHIFT 4 224 #define PIXIS_LBMAP_ALTBANK 0x40 225 226 #define CONFIG_SYS_FLASH_QUIET_TEST 227 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 228 229 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 230 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 231 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 232 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 233 234 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 235 236 #if defined(CONFIG_RAMBOOT_PBL) 237 #define CONFIG_SYS_RAMBOOT 238 #endif 239 240 /* Nand Flash */ 241 #ifdef CONFIG_NAND_FSL_ELBC 242 #define CONFIG_SYS_NAND_BASE 0xffa00000 243 #ifdef CONFIG_PHYS_64BIT 244 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 245 #else 246 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 247 #endif 248 249 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 250 #define CONFIG_SYS_MAX_NAND_DEVICE 1 251 #define CONFIG_CMD_NAND 252 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 253 254 /* NAND flash config */ 255 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 256 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 257 | BR_PS_8 /* Port Size = 8 bit */ \ 258 | BR_MS_FCM /* MSEL = FCM */ \ 259 | BR_V) /* valid */ 260 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 261 | OR_FCM_PGS /* Large Page*/ \ 262 | OR_FCM_CSCT \ 263 | OR_FCM_CST \ 264 | OR_FCM_CHT \ 265 | OR_FCM_SCY_1 \ 266 | OR_FCM_TRLX \ 267 | OR_FCM_EHTR) 268 269 #ifdef CONFIG_NAND 270 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 271 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 272 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 273 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 274 #else 275 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 276 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 277 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 278 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 279 #endif 280 #else 281 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 282 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 283 #endif /* CONFIG_NAND_FSL_ELBC */ 284 285 #define CONFIG_SYS_FLASH_EMPTY_INFO 286 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 287 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 288 289 #define CONFIG_BOARD_EARLY_INIT_F 290 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 291 #define CONFIG_MISC_INIT_R 292 293 #define CONFIG_HWCONFIG 294 295 /* define to use L1 as initial stack */ 296 #define CONFIG_L1_INIT_RAM 297 #define CONFIG_SYS_INIT_RAM_LOCK 298 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 299 #ifdef CONFIG_PHYS_64BIT 300 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 301 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 302 /* The assembler doesn't like typecast */ 303 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 304 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 305 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 306 #else 307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 309 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 310 #endif 311 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 312 313 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 314 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 315 316 #define CONFIG_SYS_MONITOR_LEN (768 * 1024) 317 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 318 319 /* Serial Port - controlled on board with jumper J8 320 * open - index 2 321 * shorted - index 1 322 */ 323 #define CONFIG_CONS_INDEX 1 324 #define CONFIG_SYS_NS16550_SERIAL 325 #define CONFIG_SYS_NS16550_REG_SIZE 1 326 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 327 328 #define CONFIG_SYS_BAUDRATE_TABLE \ 329 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 330 331 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 332 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 333 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 334 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 335 336 /* I2C */ 337 #define CONFIG_SYS_I2C 338 #define CONFIG_SYS_I2C_FSL 339 #define CONFIG_SYS_FSL_I2C_SPEED 400000 340 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 341 #define CONFIG_SYS_FSL_I2C_OFFSET 0x118000 342 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 343 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 344 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100 345 346 /* 347 * RapidIO 348 */ 349 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 350 #ifdef CONFIG_PHYS_64BIT 351 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 352 #else 353 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 354 #endif 355 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 356 357 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 358 #ifdef CONFIG_PHYS_64BIT 359 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 360 #else 361 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 362 #endif 363 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 364 365 /* 366 * for slave u-boot IMAGE instored in master memory space, 367 * PHYS must be aligned based on the SIZE 368 */ 369 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull 370 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull 371 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */ 372 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull 373 /* 374 * for slave UCODE and ENV instored in master memory space, 375 * PHYS must be aligned based on the SIZE 376 */ 377 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull 378 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull 379 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */ 380 381 /* slave core release by master*/ 382 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4 383 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */ 384 385 /* 386 * SRIO_PCIE_BOOT - SLAVE 387 */ 388 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE 389 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000 390 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \ 391 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR) 392 #endif 393 394 /* 395 * eSPI - Enhanced SPI 396 */ 397 #define CONFIG_SF_DEFAULT_SPEED 10000000 398 #define CONFIG_SF_DEFAULT_MODE 0 399 400 /* 401 * General PCI 402 * Memory space is mapped 1-1, but I/O space must start from 0. 403 */ 404 405 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 406 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 407 #ifdef CONFIG_PHYS_64BIT 408 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 409 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 410 #else 411 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 412 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 413 #endif 414 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 415 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 416 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 417 #ifdef CONFIG_PHYS_64BIT 418 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 419 #else 420 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 421 #endif 422 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 423 424 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 425 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 426 #ifdef CONFIG_PHYS_64BIT 427 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 428 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 429 #else 430 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 431 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 432 #endif 433 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 434 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 435 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 436 #ifdef CONFIG_PHYS_64BIT 437 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 438 #else 439 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 440 #endif 441 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 442 443 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 444 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 445 #ifdef CONFIG_PHYS_64BIT 446 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 447 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 448 #else 449 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 450 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 451 #endif 452 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 453 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 454 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 455 #ifdef CONFIG_PHYS_64BIT 456 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 457 #else 458 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 459 #endif 460 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 461 462 /* controller 4, Base address 203000 */ 463 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 464 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 465 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 466 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 467 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 468 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 469 470 /* Qman/Bman */ 471 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 472 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 473 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 474 #ifdef CONFIG_PHYS_64BIT 475 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 476 #else 477 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 478 #endif 479 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 480 #define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000 481 #define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000 482 #define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE 483 #define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 484 #define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \ 485 CONFIG_SYS_BMAN_CENA_SIZE) 486 #define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1) 487 #define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08 488 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 489 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 490 #ifdef CONFIG_PHYS_64BIT 491 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 492 #else 493 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 494 #endif 495 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 496 #define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000 497 #define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000 498 #define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE 499 #define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 500 #define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \ 501 CONFIG_SYS_QMAN_CENA_SIZE) 502 #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) 503 #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08 504 505 #define CONFIG_SYS_DPAA_FMAN 506 #define CONFIG_SYS_DPAA_PME 507 /* Default address of microcode for the Linux Fman driver */ 508 #if defined(CONFIG_SPIFLASH) 509 /* 510 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 511 * env, so we got 0x110000. 512 */ 513 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 514 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 515 #elif defined(CONFIG_SDCARD) 516 /* 517 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 518 * about 825KB (1650 blocks), Env is stored after the image, and the env size is 519 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. 520 */ 521 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 522 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) 523 #elif defined(CONFIG_NAND) 524 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 525 #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) 526 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) 527 /* 528 * Slave has no ucode locally, it can fetch this from remote. When implementing 529 * in two corenet boards, slave's ucode could be stored in master's memory 530 * space, the address can be mapped from slave TLB->slave LAW-> 531 * slave SRIO or PCIE outbound window->master inbound window-> 532 * master LAW->the ucode address in master's memory space. 533 */ 534 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 535 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 536 #else 537 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 538 #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 539 #endif 540 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 541 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 542 543 #ifdef CONFIG_SYS_DPAA_FMAN 544 #define CONFIG_FMAN_ENET 545 #define CONFIG_PHYLIB_10G 546 #define CONFIG_PHY_VITESSE 547 #define CONFIG_PHY_TERANETICS 548 #endif 549 550 #ifdef CONFIG_PCI 551 #define CONFIG_PCI_INDIRECT_BRIDGE 552 553 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 554 #define CONFIG_DOS_PARTITION 555 #endif /* CONFIG_PCI */ 556 557 /* SATA */ 558 #ifdef CONFIG_FSL_SATA_V2 559 #define CONFIG_LIBATA 560 #define CONFIG_FSL_SATA 561 562 #define CONFIG_SYS_SATA_MAX_DEVICE 2 563 #define CONFIG_SATA1 564 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 565 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 566 #define CONFIG_SATA2 567 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 568 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 569 570 #define CONFIG_LBA48 571 #define CONFIG_CMD_SATA 572 #define CONFIG_DOS_PARTITION 573 #endif 574 575 #ifdef CONFIG_FMAN_ENET 576 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 577 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 578 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 579 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 580 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 581 582 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 583 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 584 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 585 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 586 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 587 588 #define CONFIG_SYS_TBIPA_VALUE 8 589 #define CONFIG_MII /* MII PHY management */ 590 #define CONFIG_ETHPRIME "FM1@DTSEC1" 591 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 592 #endif 593 594 /* 595 * Environment 596 */ 597 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 598 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 599 600 /* 601 * Command line configuration. 602 */ 603 #define CONFIG_CMD_ERRATA 604 #define CONFIG_CMD_IRQ 605 #define CONFIG_CMD_REGINFO 606 607 #ifdef CONFIG_PCI 608 #define CONFIG_CMD_PCI 609 #endif 610 611 /* 612 * USB 613 */ 614 #define CONFIG_HAS_FSL_DR_USB 615 #define CONFIG_HAS_FSL_MPH_USB 616 617 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) 618 #define CONFIG_USB_EHCI 619 #define CONFIG_USB_EHCI_FSL 620 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 621 #endif 622 623 #ifdef CONFIG_MMC 624 #define CONFIG_FSL_ESDHC 625 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 626 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 627 #define CONFIG_GENERIC_MMC 628 #define CONFIG_DOS_PARTITION 629 #endif 630 631 /* Hash command with SHA acceleration supported in hardware */ 632 #ifdef CONFIG_FSL_CAAM 633 #define CONFIG_CMD_HASH 634 #define CONFIG_SHA_HW_ACCEL 635 #endif 636 637 /* 638 * Miscellaneous configurable options 639 */ 640 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 641 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 642 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 643 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 644 #ifdef CONFIG_CMD_KGDB 645 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 646 #else 647 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 648 #endif 649 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 650 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 651 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 652 653 /* 654 * For booting Linux, the board info and command line data 655 * have to be in the first 64 MB of memory, since this is 656 * the maximum mapped by the Linux kernel during initialization. 657 */ 658 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 659 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 660 661 #ifdef CONFIG_CMD_KGDB 662 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 663 #endif 664 665 /* 666 * Environment Configuration 667 */ 668 #define CONFIG_ROOTPATH "/opt/nfsroot" 669 #define CONFIG_BOOTFILE "uImage" 670 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 671 672 /* default location for tftp and bootm */ 673 #define CONFIG_LOADADDR 1000000 674 675 676 #define CONFIG_BAUDRATE 115200 677 678 #ifdef CONFIG_TARGET_P4080DS 679 #define __USB_PHY_TYPE ulpi 680 #else 681 #define __USB_PHY_TYPE utmi 682 #endif 683 684 #define CONFIG_EXTRA_ENV_SETTINGS \ 685 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 686 "bank_intlv=cs0_cs1;" \ 687 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\ 688 "usb2:dr_mode=peripheral,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ 689 "netdev=eth0\0" \ 690 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 691 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 692 "tftpflash=tftpboot $loadaddr $uboot && " \ 693 "protect off $ubootaddr +$filesize && " \ 694 "erase $ubootaddr +$filesize && " \ 695 "cp.b $loadaddr $ubootaddr $filesize && " \ 696 "protect on $ubootaddr +$filesize && " \ 697 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 698 "consoledev=ttyS0\0" \ 699 "ramdiskaddr=2000000\0" \ 700 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 701 "fdtaddr=1e00000\0" \ 702 "fdtfile=p4080ds/p4080ds.dtb\0" \ 703 "bdev=sda3\0" 704 705 #define CONFIG_HDBOOT \ 706 "setenv bootargs root=/dev/$bdev rw " \ 707 "console=$consoledev,$baudrate $othbootargs;" \ 708 "tftp $loadaddr $bootfile;" \ 709 "tftp $fdtaddr $fdtfile;" \ 710 "bootm $loadaddr - $fdtaddr" 711 712 #define CONFIG_NFSBOOTCOMMAND \ 713 "setenv bootargs root=/dev/nfs rw " \ 714 "nfsroot=$serverip:$rootpath " \ 715 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 716 "console=$consoledev,$baudrate $othbootargs;" \ 717 "tftp $loadaddr $bootfile;" \ 718 "tftp $fdtaddr $fdtfile;" \ 719 "bootm $loadaddr - $fdtaddr" 720 721 #define CONFIG_RAMBOOTCOMMAND \ 722 "setenv bootargs root=/dev/ram rw " \ 723 "console=$consoledev,$baudrate $othbootargs;" \ 724 "tftp $ramdiskaddr $ramdiskfile;" \ 725 "tftp $loadaddr $bootfile;" \ 726 "tftp $fdtaddr $fdtfile;" \ 727 "bootm $loadaddr $ramdiskaddr $fdtaddr" 728 729 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 730 731 #include <asm/fsl_secure_boot.h> 732 733 #endif /* __CONFIG_H */ 734