1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #include "../board/freescale/common/ics307_clk.h" 30 31 #ifdef CONFIG_RAMBOOT_PBL 32 #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE 33 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 34 #endif 35 36 #ifdef CONFIG_SRIOBOOT_SLAVE 37 /* Set 1M boot space */ 38 #define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) 39 #define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \ 40 (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR) 41 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc 42 #define CONFIG_SYS_NO_FLASH 43 #endif 44 45 /* High Level Configuration Options */ 46 #define CONFIG_BOOKE 47 #define CONFIG_E500 /* BOOKE e500 family */ 48 #define CONFIG_E500MC /* BOOKE e500mc family */ 49 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 50 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 51 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 52 #define CONFIG_MP /* support multiple processors */ 53 54 #ifndef CONFIG_SYS_TEXT_BASE 55 #define CONFIG_SYS_TEXT_BASE 0xeff80000 56 #endif 57 58 #ifndef CONFIG_RESET_VECTOR_ADDRESS 59 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 60 #endif 61 62 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 63 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 64 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 65 #define CONFIG_PCI /* Enable PCI/PCIE */ 66 #define CONFIG_PCIE1 /* PCIE controler 1 */ 67 #define CONFIG_PCIE2 /* PCIE controler 2 */ 68 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 69 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 70 71 #define CONFIG_SYS_SRIO 72 #define CONFIG_SRIO1 /* SRIO port 1 */ 73 #define CONFIG_SRIO2 /* SRIO port 2 */ 74 75 #define CONFIG_FSL_LAW /* Use common FSL init code */ 76 77 #define CONFIG_ENV_OVERWRITE 78 79 #ifdef CONFIG_SYS_NO_FLASH 80 #define CONFIG_ENV_IS_NOWHERE 81 #else 82 #define CONFIG_FLASH_CFI_DRIVER 83 #define CONFIG_SYS_FLASH_CFI 84 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 85 #endif 86 87 #if defined(CONFIG_SPIFLASH) 88 #define CONFIG_SYS_EXTRA_ENV_RELOC 89 #define CONFIG_ENV_IS_IN_SPI_FLASH 90 #define CONFIG_ENV_SPI_BUS 0 91 #define CONFIG_ENV_SPI_CS 0 92 #define CONFIG_ENV_SPI_MAX_HZ 10000000 93 #define CONFIG_ENV_SPI_MODE 0 94 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 95 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 96 #define CONFIG_ENV_SECT_SIZE 0x10000 97 #elif defined(CONFIG_SDCARD) 98 #define CONFIG_SYS_EXTRA_ENV_RELOC 99 #define CONFIG_ENV_IS_IN_MMC 100 #define CONFIG_FSL_FIXED_MMC_LOCATION 101 #define CONFIG_SYS_MMC_ENV_DEV 0 102 #define CONFIG_ENV_SIZE 0x2000 103 #define CONFIG_ENV_OFFSET (512 * 1097) 104 #elif defined(CONFIG_NAND) 105 #define CONFIG_SYS_EXTRA_ENV_RELOC 106 #define CONFIG_ENV_IS_IN_NAND 107 #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE 108 #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) 109 #elif defined(CONFIG_ENV_IS_NOWHERE) 110 #define CONFIG_ENV_SIZE 0x2000 111 #else 112 #define CONFIG_ENV_IS_IN_FLASH 113 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 114 #define CONFIG_ENV_SIZE 0x2000 115 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 116 #endif 117 118 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 119 120 /* 121 * These can be toggled for performance analysis, otherwise use default. 122 */ 123 #define CONFIG_SYS_CACHE_STASHING 124 #define CONFIG_BACKSIDE_L2_CACHE 125 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 126 #define CONFIG_BTB /* toggle branch predition */ 127 #define CONFIG_DDR_ECC 128 #ifdef CONFIG_DDR_ECC 129 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 130 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 131 #endif 132 133 #define CONFIG_ENABLE_36BIT_PHYS 134 135 #ifdef CONFIG_PHYS_64BIT 136 #define CONFIG_ADDR_MAP 137 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 138 #endif 139 140 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 141 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 142 #define CONFIG_SYS_MEMTEST_END 0x00400000 143 #define CONFIG_SYS_ALT_MEMTEST 144 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 145 146 /* 147 * Config the L3 Cache as L3 SRAM 148 */ 149 #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE 150 #ifdef CONFIG_PHYS_64BIT 151 #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) 152 #else 153 #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR 154 #endif 155 #define CONFIG_SYS_L3_SIZE (1024 << 10) 156 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) 157 158 #ifdef CONFIG_PHYS_64BIT 159 #define CONFIG_SYS_DCSRBAR 0xf0000000 160 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 161 #endif 162 163 /* EEPROM */ 164 #define CONFIG_ID_EEPROM 165 #define CONFIG_SYS_I2C_EEPROM_NXID 166 #define CONFIG_SYS_EEPROM_BUS_NUM 0 167 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 168 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 169 170 /* 171 * DDR Setup 172 */ 173 #define CONFIG_VERY_BIG_RAM 174 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 175 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 176 177 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 178 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 179 180 #define CONFIG_DDR_SPD 181 #define CONFIG_FSL_DDR3 182 183 #ifdef CONFIG_P3060QDS 184 #define CONFIG_SYS_SPD_BUS_NUM 0 185 #else 186 #define CONFIG_SYS_SPD_BUS_NUM 1 187 #endif 188 #define SPD_EEPROM_ADDRESS1 0x51 189 #define SPD_EEPROM_ADDRESS2 0x52 190 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ 191 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 192 193 /* 194 * Local Bus Definitions 195 */ 196 197 /* Set the local bus clock 1/8 of platform clock */ 198 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 199 200 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 201 #ifdef CONFIG_PHYS_64BIT 202 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 203 #else 204 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 205 #endif 206 207 #define CONFIG_SYS_FLASH_BR_PRELIM \ 208 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ 209 | BR_PS_16 | BR_V) 210 #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 211 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 212 213 #define CONFIG_SYS_BR1_PRELIM \ 214 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 215 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 216 217 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 218 #ifdef CONFIG_PHYS_64BIT 219 #define PIXIS_BASE_PHYS 0xfffdf0000ull 220 #else 221 #define PIXIS_BASE_PHYS PIXIS_BASE 222 #endif 223 224 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 225 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 226 227 #define PIXIS_LBMAP_SWITCH 7 228 #define PIXIS_LBMAP_MASK 0xf0 229 #define PIXIS_LBMAP_SHIFT 4 230 #define PIXIS_LBMAP_ALTBANK 0x40 231 232 #define CONFIG_SYS_FLASH_QUIET_TEST 233 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 234 235 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 236 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 237 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 238 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 239 240 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 241 242 #if defined(CONFIG_RAMBOOT_PBL) 243 #define CONFIG_SYS_RAMBOOT 244 #endif 245 246 /* Nand Flash */ 247 #ifdef CONFIG_NAND_FSL_ELBC 248 #define CONFIG_SYS_NAND_BASE 0xffa00000 249 #ifdef CONFIG_PHYS_64BIT 250 #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull 251 #else 252 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE 253 #endif 254 255 #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} 256 #define CONFIG_SYS_MAX_NAND_DEVICE 1 257 #define CONFIG_MTD_NAND_VERIFY_WRITE 258 #define CONFIG_CMD_NAND 259 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 260 261 /* NAND flash config */ 262 #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ 263 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ 264 | BR_PS_8 /* Port Size = 8 bit */ \ 265 | BR_MS_FCM /* MSEL = FCM */ \ 266 | BR_V) /* valid */ 267 #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ 268 | OR_FCM_PGS /* Large Page*/ \ 269 | OR_FCM_CSCT \ 270 | OR_FCM_CST \ 271 | OR_FCM_CHT \ 272 | OR_FCM_SCY_1 \ 273 | OR_FCM_TRLX \ 274 | OR_FCM_EHTR) 275 276 #ifdef CONFIG_NAND 277 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 278 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 279 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 280 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 281 #else 282 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 283 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 284 #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ 285 #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ 286 #endif 287 #else 288 #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ 289 #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ 290 #endif /* CONFIG_NAND_FSL_ELBC */ 291 292 #define CONFIG_SYS_FLASH_EMPTY_INFO 293 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 294 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 295 296 #define CONFIG_BOARD_EARLY_INIT_F 297 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 298 #define CONFIG_MISC_INIT_R 299 300 #define CONFIG_HWCONFIG 301 302 /* define to use L1 as initial stack */ 303 #define CONFIG_L1_INIT_RAM 304 #define CONFIG_SYS_INIT_RAM_LOCK 305 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 306 #ifdef CONFIG_PHYS_64BIT 307 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 308 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 309 /* The assembler doesn't like typecast */ 310 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 311 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 312 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 313 #else 314 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 315 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 316 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 317 #endif 318 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 319 320 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 321 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 322 323 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 324 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 325 326 /* Serial Port - controlled on board with jumper J8 327 * open - index 2 328 * shorted - index 1 329 */ 330 #define CONFIG_CONS_INDEX 1 331 #define CONFIG_SYS_NS16550 332 #define CONFIG_SYS_NS16550_SERIAL 333 #define CONFIG_SYS_NS16550_REG_SIZE 1 334 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 335 336 #define CONFIG_SYS_BAUDRATE_TABLE \ 337 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 338 339 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 340 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 341 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 342 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 343 344 /* Use the HUSH parser */ 345 #define CONFIG_SYS_HUSH_PARSER 346 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 347 348 /* pass open firmware flat tree */ 349 #define CONFIG_OF_LIBFDT 350 #define CONFIG_OF_BOARD_SETUP 351 #define CONFIG_OF_STDOUT_VIA_ALIAS 352 353 /* new uImage format support */ 354 #define CONFIG_FIT 355 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 356 357 /* I2C */ 358 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 359 #define CONFIG_HARD_I2C /* I2C with hardware support */ 360 #define CONFIG_I2C_MULTI_BUS 361 #define CONFIG_I2C_CMD_TREE 362 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 363 #define CONFIG_SYS_I2C_SLAVE 0x7F 364 #define CONFIG_SYS_I2C_OFFSET 0x118000 365 #define CONFIG_SYS_I2C2_OFFSET 0x118100 366 367 /* 368 * RapidIO 369 */ 370 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 371 #ifdef CONFIG_PHYS_64BIT 372 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 373 #else 374 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 375 #endif 376 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 377 378 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 379 #ifdef CONFIG_PHYS_64BIT 380 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 381 #else 382 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 383 #endif 384 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 385 386 /* 387 * SRIOBOOT - MASTER 388 */ 389 #ifdef CONFIG_SRIOBOOT_MASTER 390 /* master port for srioboot*/ 391 #define CONFIG_SRIOBOOT_MASTER_PORT 0 392 /* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */ 393 /* 394 * for slave u-boot IMAGE instored in master memory space, 395 * PHYS must be aligned based on the SIZE 396 */ 397 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull 398 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull 399 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */ 400 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull 401 #define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull 402 #endif 403 404 /* 405 * SRIOBOOT - SLAVE 406 */ 407 #ifdef CONFIG_SRIOBOOT_SLAVE 408 /* slave port for srioboot */ 409 #define CONFIG_SRIOBOOT_SLAVE_PORT0 410 /* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */ 411 #endif 412 413 /* 414 * eSPI - Enhanced SPI 415 */ 416 #define CONFIG_FSL_ESPI 417 #define CONFIG_SPI_FLASH 418 #define CONFIG_SPI_FLASH_SPANSION 419 #define CONFIG_CMD_SF 420 #define CONFIG_SF_DEFAULT_SPEED 10000000 421 #define CONFIG_SF_DEFAULT_MODE 0 422 423 /* 424 * General PCI 425 * Memory space is mapped 1-1, but I/O space must start from 0. 426 */ 427 428 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 429 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 430 #ifdef CONFIG_PHYS_64BIT 431 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 432 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 433 #else 434 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 435 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 436 #endif 437 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 438 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 439 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 440 #ifdef CONFIG_PHYS_64BIT 441 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 442 #else 443 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 444 #endif 445 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 446 447 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 448 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 449 #ifdef CONFIG_PHYS_64BIT 450 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 451 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 452 #else 453 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 454 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 455 #endif 456 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 457 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 458 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 459 #ifdef CONFIG_PHYS_64BIT 460 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 461 #else 462 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 463 #endif 464 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 465 466 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 467 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 468 #ifdef CONFIG_PHYS_64BIT 469 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 470 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 471 #else 472 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 473 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 474 #endif 475 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 476 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 477 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 478 #ifdef CONFIG_PHYS_64BIT 479 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 480 #else 481 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 482 #endif 483 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 484 485 /* controller 4, Base address 203000 */ 486 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 487 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 488 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 489 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 490 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 491 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 492 493 /* Qman/Bman */ 494 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 495 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 496 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 497 #ifdef CONFIG_PHYS_64BIT 498 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 499 #else 500 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 501 #endif 502 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 503 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 504 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 505 #ifdef CONFIG_PHYS_64BIT 506 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 507 #else 508 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 509 #endif 510 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 511 512 #define CONFIG_SYS_DPAA_FMAN 513 #define CONFIG_SYS_DPAA_PME 514 /* Default address of microcode for the Linux Fman driver */ 515 #if defined(CONFIG_SPIFLASH) 516 /* 517 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after 518 * env, so we got 0x110000. 519 */ 520 #define CONFIG_SYS_QE_FW_IN_SPIFLASH 521 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 522 #elif defined(CONFIG_SDCARD) 523 /* 524 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is 525 * about 545KB (1089 blocks), Env is stored after the image, and the env size is 526 * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. 527 */ 528 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC 529 #define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) 530 #elif defined(CONFIG_NAND) 531 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND 532 #define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) 533 #elif defined(CONFIG_SRIOBOOT_SLAVE) 534 /* 535 * Slave has no ucode locally, it can fetch this from remote. When implementing 536 * in two corenet boards, slave's ucode could be stored in master's memory 537 * space, the address can be mapped from slave TLB->slave LAW-> 538 * slave SRIO outbound window->master inbound window->master LAW-> 539 * the ucode address in master's NOR flash. 540 */ 541 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE 542 #define CONFIG_SYS_QE_FMAN_FW_ADDR NULL 543 #else 544 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR 545 #define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 546 #endif 547 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 548 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) 549 550 #ifdef CONFIG_SYS_DPAA_FMAN 551 #define CONFIG_FMAN_ENET 552 #define CONFIG_PHYLIB_10G 553 #define CONFIG_PHY_VITESSE 554 #define CONFIG_PHY_TERANETICS 555 #endif 556 557 #ifdef CONFIG_PCI 558 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 559 #define CONFIG_E1000 560 561 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 562 #define CONFIG_DOS_PARTITION 563 #endif /* CONFIG_PCI */ 564 565 /* SATA */ 566 #ifdef CONFIG_FSL_SATA_V2 567 #define CONFIG_LIBATA 568 #define CONFIG_FSL_SATA 569 570 #define CONFIG_SYS_SATA_MAX_DEVICE 2 571 #define CONFIG_SATA1 572 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 573 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 574 #define CONFIG_SATA2 575 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 576 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 577 578 #define CONFIG_LBA48 579 #define CONFIG_CMD_SATA 580 #define CONFIG_DOS_PARTITION 581 #define CONFIG_CMD_EXT2 582 #endif 583 584 #ifdef CONFIG_FMAN_ENET 585 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 586 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 587 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 588 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 589 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 590 591 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 592 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 593 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 594 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 595 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 596 597 #define CONFIG_SYS_TBIPA_VALUE 8 598 #define CONFIG_MII /* MII PHY management */ 599 #define CONFIG_ETHPRIME "FM1@DTSEC1" 600 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 601 #endif 602 603 /* 604 * Environment 605 */ 606 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 607 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 608 609 /* 610 * Command line configuration. 611 */ 612 #include <config_cmd_default.h> 613 614 #define CONFIG_CMD_DHCP 615 #define CONFIG_CMD_ELF 616 #define CONFIG_CMD_ERRATA 617 #define CONFIG_CMD_GREPENV 618 #define CONFIG_CMD_IRQ 619 #define CONFIG_CMD_I2C 620 #define CONFIG_CMD_MII 621 #define CONFIG_CMD_PING 622 #define CONFIG_CMD_SETEXPR 623 #define CONFIG_CMD_REGINFO 624 625 #ifdef CONFIG_PCI 626 #define CONFIG_CMD_PCI 627 #define CONFIG_CMD_NET 628 #endif 629 630 /* 631 * USB 632 */ 633 #define CONFIG_CMD_USB 634 #define CONFIG_USB_STORAGE 635 #define CONFIG_USB_EHCI 636 #define CONFIG_USB_EHCI_FSL 637 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 638 #define CONFIG_CMD_EXT2 639 #define CONFIG_HAS_FSL_DR_USB 640 641 #ifdef CONFIG_MMC 642 #define CONFIG_FSL_ESDHC 643 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 644 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 645 #define CONFIG_CMD_MMC 646 #define CONFIG_GENERIC_MMC 647 #define CONFIG_CMD_EXT2 648 #define CONFIG_CMD_FAT 649 #define CONFIG_DOS_PARTITION 650 #endif 651 652 /* 653 * Miscellaneous configurable options 654 */ 655 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 656 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 657 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 658 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 659 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 660 #ifdef CONFIG_CMD_KGDB 661 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 662 #else 663 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 664 #endif 665 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 666 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 667 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 668 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 669 670 /* 671 * For booting Linux, the board info and command line data 672 * have to be in the first 64 MB of memory, since this is 673 * the maximum mapped by the Linux kernel during initialization. 674 */ 675 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ 676 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 677 678 #ifdef CONFIG_CMD_KGDB 679 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 680 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 681 #endif 682 683 /* 684 * Environment Configuration 685 */ 686 #define CONFIG_ROOTPATH "/opt/nfsroot" 687 #define CONFIG_BOOTFILE "uImage" 688 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 689 690 /* default location for tftp and bootm */ 691 #define CONFIG_LOADADDR 1000000 692 693 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 694 695 #define CONFIG_BAUDRATE 115200 696 697 #if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS) 698 #define __USB_PHY_TYPE ulpi 699 #else 700 #define __USB_PHY_TYPE utmi 701 #endif 702 703 #define CONFIG_EXTRA_ENV_SETTINGS \ 704 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 705 "bank_intlv=cs0_cs1;" \ 706 "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\ 707 "netdev=eth0\0" \ 708 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 709 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ 710 "tftpflash=tftpboot $loadaddr $uboot && " \ 711 "protect off $ubootaddr +$filesize && " \ 712 "erase $ubootaddr +$filesize && " \ 713 "cp.b $loadaddr $ubootaddr $filesize && " \ 714 "protect on $ubootaddr +$filesize && " \ 715 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 716 "consoledev=ttyS0\0" \ 717 "ramdiskaddr=2000000\0" \ 718 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 719 "fdtaddr=c00000\0" \ 720 "fdtfile=p4080ds/p4080ds.dtb\0" \ 721 "bdev=sda3\0" \ 722 "c=ffe\0" 723 724 #define CONFIG_HDBOOT \ 725 "setenv bootargs root=/dev/$bdev rw " \ 726 "console=$consoledev,$baudrate $othbootargs;" \ 727 "tftp $loadaddr $bootfile;" \ 728 "tftp $fdtaddr $fdtfile;" \ 729 "bootm $loadaddr - $fdtaddr" 730 731 #define CONFIG_NFSBOOTCOMMAND \ 732 "setenv bootargs root=/dev/nfs rw " \ 733 "nfsroot=$serverip:$rootpath " \ 734 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 735 "console=$consoledev,$baudrate $othbootargs;" \ 736 "tftp $loadaddr $bootfile;" \ 737 "tftp $fdtaddr $fdtfile;" \ 738 "bootm $loadaddr - $fdtaddr" 739 740 #define CONFIG_RAMBOOTCOMMAND \ 741 "setenv bootargs root=/dev/ram rw " \ 742 "console=$consoledev,$baudrate $othbootargs;" \ 743 "tftp $ramdiskaddr $ramdiskfile;" \ 744 "tftp $loadaddr $bootfile;" \ 745 "tftp $fdtaddr $fdtfile;" \ 746 "bootm $loadaddr $ramdiskaddr $fdtaddr" 747 748 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 749 750 #ifdef CONFIG_SECURE_BOOT 751 #include <asm/fsl_secure_boot.h> 752 #endif 753 754 #endif /* __CONFIG_H */ 755