1 /* 2 * Copyright 2009-2011 Freescale Semiconductor, Inc. 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 /* 24 * Corenet DS style board configuration file 25 */ 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #include "../board/freescale/common/ics307_clk.h" 30 31 /* High Level Configuration Options */ 32 #define CONFIG_BOOKE 33 #define CONFIG_E500 /* BOOKE e500 family */ 34 #define CONFIG_E500MC /* BOOKE e500mc family */ 35 #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ 36 #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ 37 #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ 38 #define CONFIG_MP /* support multiple processors */ 39 40 #ifndef CONFIG_SYS_TEXT_BASE 41 #define CONFIG_SYS_TEXT_BASE 0xeff80000 42 #endif 43 44 #ifndef CONFIG_RESET_VECTOR_ADDRESS 45 #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc 46 #endif 47 48 #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ 49 #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS 50 #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ 51 #define CONFIG_PCI /* Enable PCI/PCIE */ 52 #define CONFIG_PCIE1 /* PCIE controler 1 */ 53 #define CONFIG_PCIE2 /* PCIE controler 2 */ 54 #define CONFIG_PCIE3 /* PCIE controler 3 */ 55 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 56 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 57 58 #define CONFIG_SYS_SRIO 59 #define CONFIG_SRIO1 /* SRIO port 1 */ 60 #define CONFIG_SRIO2 /* SRIO port 2 */ 61 62 #define CONFIG_FSL_LAW /* Use common FSL init code */ 63 64 #define CONFIG_ENV_OVERWRITE 65 66 #ifdef CONFIG_SYS_NO_FLASH 67 #define CONFIG_ENV_IS_NOWHERE 68 #else 69 #define CONFIG_ENV_IS_IN_FLASH 70 #define CONFIG_FLASH_CFI_DRIVER 71 #define CONFIG_SYS_FLASH_CFI 72 #endif 73 74 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ 75 76 /* 77 * These can be toggled for performance analysis, otherwise use default. 78 */ 79 #define CONFIG_SYS_CACHE_STASHING 80 #define CONFIG_BACKSIDE_L2_CACHE 81 #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E 82 #define CONFIG_BTB /* toggle branch predition */ 83 #define CONFIG_DDR_ECC 84 #ifdef CONFIG_DDR_ECC 85 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER 86 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef 87 #endif 88 89 #define CONFIG_ENABLE_36BIT_PHYS 90 91 #ifdef CONFIG_PHYS_64BIT 92 #define CONFIG_ADDR_MAP 93 #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ 94 #endif 95 96 #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ 97 #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ 98 #define CONFIG_SYS_MEMTEST_END 0x00400000 99 #define CONFIG_SYS_ALT_MEMTEST 100 #define CONFIG_PANIC_HANG /* do not reset board on panic */ 101 102 /* 103 * Base addresses -- Note these are effective addresses where the 104 * actual resources get mapped (not physical addresses) 105 */ 106 #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ 107 #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ 108 #ifdef CONFIG_PHYS_64BIT 109 #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ 110 #else 111 #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 112 #endif 113 #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 114 115 #ifdef CONFIG_PHYS_64BIT 116 #define CONFIG_SYS_DCSRBAR 0xf0000000 117 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull 118 #endif 119 120 /* EEPROM */ 121 #define CONFIG_ID_EEPROM 122 #define CONFIG_SYS_I2C_EEPROM_NXID 123 #define CONFIG_SYS_EEPROM_BUS_NUM 0 124 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 125 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 126 127 /* 128 * DDR Setup 129 */ 130 #define CONFIG_VERY_BIG_RAM 131 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 132 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 133 134 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 135 #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) 136 137 #define CONFIG_DDR_SPD 138 #define CONFIG_FSL_DDR3 139 140 #define CONFIG_SYS_SPD_BUS_NUM 1 141 #define SPD_EEPROM_ADDRESS1 0x51 142 #define SPD_EEPROM_ADDRESS2 0x52 143 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ 144 145 /* 146 * Local Bus Definitions 147 */ 148 149 /* Set the local bus clock 1/8 of platform clock */ 150 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 151 152 #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ 153 #ifdef CONFIG_PHYS_64BIT 154 #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull 155 #else 156 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE 157 #endif 158 159 #define CONFIG_SYS_BR0_PRELIM \ 160 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ 161 BR_PS_16 | BR_V) 162 #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ 163 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) 164 165 #define CONFIG_SYS_BR1_PRELIM \ 166 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) 167 #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 168 169 #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ 170 #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ 171 #ifdef CONFIG_PHYS_64BIT 172 #define PIXIS_BASE_PHYS 0xfffdf0000ull 173 #else 174 #define PIXIS_BASE_PHYS PIXIS_BASE 175 #endif 176 177 #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) 178 #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ 179 180 #define PIXIS_LBMAP_SWITCH 7 181 #define PIXIS_LBMAP_MASK 0xf0 182 #define PIXIS_LBMAP_SHIFT 4 183 #define PIXIS_LBMAP_ALTBANK 0x40 184 185 #define CONFIG_SYS_FLASH_QUIET_TEST 186 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ 187 188 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ 189 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ 190 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ 191 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ 192 193 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ 194 195 #define CONFIG_SYS_FLASH_EMPTY_INFO 196 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 197 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} 198 199 #define CONFIG_BOARD_EARLY_INIT_F 200 #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ 201 #define CONFIG_MISC_INIT_R 202 203 #define CONFIG_HWCONFIG 204 205 /* define to use L1 as initial stack */ 206 #define CONFIG_L1_INIT_RAM 207 #define CONFIG_SYS_INIT_RAM_LOCK 208 #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ 209 #ifdef CONFIG_PHYS_64BIT 210 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf 211 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR 212 /* The assembler doesn't like typecast */ 213 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ 214 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ 215 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) 216 #else 217 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ 218 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 219 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS 220 #endif 221 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ 222 223 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 224 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 225 226 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 227 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ 228 229 /* Serial Port - controlled on board with jumper J8 230 * open - index 2 231 * shorted - index 1 232 */ 233 #define CONFIG_CONS_INDEX 1 234 #define CONFIG_SYS_NS16550 235 #define CONFIG_SYS_NS16550_SERIAL 236 #define CONFIG_SYS_NS16550_REG_SIZE 1 237 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) 238 239 #define CONFIG_SYS_BAUDRATE_TABLE \ 240 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 241 242 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) 243 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) 244 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) 245 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) 246 247 /* Use the HUSH parser */ 248 #define CONFIG_SYS_HUSH_PARSER 249 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 250 251 /* pass open firmware flat tree */ 252 #define CONFIG_OF_LIBFDT 253 #define CONFIG_OF_BOARD_SETUP 254 #define CONFIG_OF_STDOUT_VIA_ALIAS 255 256 /* new uImage format support */ 257 #define CONFIG_FIT 258 #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ 259 260 /* I2C */ 261 #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 262 #define CONFIG_HARD_I2C /* I2C with hardware support */ 263 #define CONFIG_I2C_MULTI_BUS 264 #define CONFIG_I2C_CMD_TREE 265 #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 266 #define CONFIG_SYS_I2C_SLAVE 0x7F 267 #define CONFIG_SYS_I2C_OFFSET 0x118000 268 #define CONFIG_SYS_I2C2_OFFSET 0x118100 269 270 /* 271 * RapidIO 272 */ 273 #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 274 #ifdef CONFIG_PHYS_64BIT 275 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull 276 #else 277 #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 278 #endif 279 #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ 280 281 #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 282 #ifdef CONFIG_PHYS_64BIT 283 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull 284 #else 285 #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 286 #endif 287 #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ 288 289 /* 290 * General PCI 291 * Memory space is mapped 1-1, but I/O space must start from 0. 292 */ 293 294 /* controller 1, direct to uli, tgtid 3, Base address 20000 */ 295 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 296 #ifdef CONFIG_PHYS_64BIT 297 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 298 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull 299 #else 300 #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 301 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 302 #endif 303 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 304 #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 305 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 306 #ifdef CONFIG_PHYS_64BIT 307 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull 308 #else 309 #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 310 #endif 311 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 312 313 /* controller 2, Slot 2, tgtid 2, Base address 201000 */ 314 #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 315 #ifdef CONFIG_PHYS_64BIT 316 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 317 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull 318 #else 319 #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 320 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 321 #endif 322 #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ 323 #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 324 #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 325 #ifdef CONFIG_PHYS_64BIT 326 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull 327 #else 328 #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 329 #endif 330 #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ 331 332 /* controller 3, Slot 1, tgtid 1, Base address 202000 */ 333 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xe0000000 334 #ifdef CONFIG_PHYS_64BIT 335 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 336 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull 337 #else 338 #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 339 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 340 #endif 341 #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ 342 #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 343 #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 344 #ifdef CONFIG_PHYS_64BIT 345 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull 346 #else 347 #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 348 #endif 349 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ 350 351 /* controller 4, Base address 203000 */ 352 #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 353 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull 354 #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ 355 #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 356 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull 357 #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ 358 359 /* Qman/Bman */ 360 #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ 361 #define CONFIG_SYS_BMAN_NUM_PORTALS 10 362 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 363 #ifdef CONFIG_PHYS_64BIT 364 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull 365 #else 366 #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE 367 #endif 368 #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 369 #define CONFIG_SYS_QMAN_NUM_PORTALS 10 370 #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 371 #ifdef CONFIG_PHYS_64BIT 372 #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull 373 #else 374 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE 375 #endif 376 #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 377 378 #define CONFIG_SYS_DPAA_FMAN 379 #define CONFIG_SYS_DPAA_PME 380 /* Default address of microcode for the Linux Fman driver */ 381 #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 382 #ifdef CONFIG_PHYS_64BIT 383 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL 384 #else 385 #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR 386 #endif 387 388 #ifdef CONFIG_SYS_DPAA_FMAN 389 #define CONFIG_FMAN_ENET 390 #endif 391 392 #ifdef CONFIG_PCI 393 394 /*PCIE video card used*/ 395 #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT 396 397 /* video */ 398 #define CONFIG_VIDEO 399 400 #ifdef CONFIG_VIDEO 401 #define CONFIG_BIOSEMU 402 #define CONFIG_CFB_CONSOLE 403 #define CONFIG_VIDEO_SW_CURSOR 404 #define CONFIG_VGA_AS_SINGLE_DEVICE 405 #define CONFIG_ATI_RADEON_FB 406 #define CONFIG_VIDEO_LOGO 407 #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET 408 #endif 409 410 #define CONFIG_NET_MULTI 411 #define CONFIG_PCI_PNP /* do pci plug-and-play */ 412 #define CONFIG_E1000 413 414 #ifndef CONFIG_PCI_PNP 415 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS 416 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS 417 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ 418 #endif 419 420 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 421 #define CONFIG_DOS_PARTITION 422 #endif /* CONFIG_PCI */ 423 424 /* SATA */ 425 #ifdef CONFIG_FSL_SATA_V2 426 #define CONFIG_LIBATA 427 #define CONFIG_FSL_SATA 428 429 #define CONFIG_SYS_SATA_MAX_DEVICE 2 430 #define CONFIG_SATA1 431 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 432 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 433 #define CONFIG_SATA2 434 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 435 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 436 437 #define CONFIG_LBA48 438 #define CONFIG_CMD_SATA 439 #define CONFIG_DOS_PARTITION 440 #define CONFIG_CMD_EXT2 441 #endif 442 443 #ifdef CONFIG_FMAN_ENET 444 #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c 445 #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d 446 #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e 447 #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f 448 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 449 450 #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c 451 #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d 452 #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e 453 #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f 454 #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 455 456 #define CONFIG_SYS_TBIPA_VALUE 8 457 #define CONFIG_MII /* MII PHY management */ 458 #define CONFIG_ETHPRIME "FM1@DTSEC1" 459 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 460 #endif 461 462 /* 463 * Environment 464 */ 465 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) 466 #define CONFIG_ENV_SIZE 0x2000 467 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ 468 469 #define CONFIG_LOADS_ECHO /* echo on for serial download */ 470 #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ 471 472 /* 473 * Command line configuration. 474 */ 475 #include <config_cmd_default.h> 476 477 #define CONFIG_CMD_ELF 478 #define CONFIG_CMD_ERRATA 479 #define CONFIG_CMD_IRQ 480 #define CONFIG_CMD_I2C 481 #define CONFIG_CMD_MII 482 #define CONFIG_CMD_PING 483 #define CONFIG_CMD_SETEXPR 484 #define CONFIG_CMD_DHCP 485 486 #ifdef CONFIG_PCI 487 #define CONFIG_CMD_PCI 488 #define CONFIG_CMD_NET 489 #endif 490 491 /* 492 * USB 493 */ 494 #define CONFIG_CMD_USB 495 #define CONFIG_USB_STORAGE 496 #define CONFIG_USB_EHCI 497 #define CONFIG_USB_EHCI_FSL 498 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 499 #define CONFIG_CMD_EXT2 500 501 #define CONFIG_MMC 502 503 #ifdef CONFIG_MMC 504 #define CONFIG_FSL_ESDHC 505 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 506 #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT 507 #define CONFIG_CMD_MMC 508 #define CONFIG_GENERIC_MMC 509 #define CONFIG_CMD_EXT2 510 #define CONFIG_CMD_FAT 511 #define CONFIG_DOS_PARTITION 512 #endif 513 514 /* 515 * Miscellaneous configurable options 516 */ 517 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 518 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 519 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 520 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 521 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 522 #ifdef CONFIG_CMD_KGDB 523 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 524 #else 525 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 526 #endif 527 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 528 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 529 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 530 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ 531 532 /* 533 * For booting Linux, the board info and command line data 534 * have to be in the first 16 MB of memory, since this is 535 * the maximum mapped by the Linux kernel during initialization. 536 */ 537 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ 538 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ 539 540 #ifdef CONFIG_CMD_KGDB 541 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 542 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 543 #endif 544 545 /* 546 * Environment Configuration 547 */ 548 #define CONFIG_ROOTPATH /opt/nfsroot 549 #define CONFIG_BOOTFILE uImage 550 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ 551 552 /* default location for tftp and bootm */ 553 #define CONFIG_LOADADDR 1000000 554 555 #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ 556 557 #define CONFIG_BAUDRATE 115200 558 559 #define CONFIG_EXTRA_ENV_SETTINGS \ 560 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ 561 "bank_intlv=cs0_cs1\0" \ 562 "netdev=eth0\0" \ 563 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ 564 "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ 565 "tftpflash=tftpboot $loadaddr $uboot && " \ 566 "protect off $ubootaddr +$filesize && " \ 567 "erase $ubootaddr +$filesize && " \ 568 "cp.b $loadaddr $ubootaddr $filesize && " \ 569 "protect on $ubootaddr +$filesize && " \ 570 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 571 "consoledev=ttyS0\0" \ 572 "ramdiskaddr=2000000\0" \ 573 "ramdiskfile=p4080ds/ramdisk.uboot\0" \ 574 "fdtaddr=c00000\0" \ 575 "fdtfile=p4080ds/p4080ds.dtb\0" \ 576 "bdev=sda3\0" \ 577 "c=ffe\0" \ 578 "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0" 579 580 #define CONFIG_HDBOOT \ 581 "setenv bootargs root=/dev/$bdev rw " \ 582 "console=$consoledev,$baudrate $othbootargs;" \ 583 "tftp $loadaddr $bootfile;" \ 584 "tftp $fdtaddr $fdtfile;" \ 585 "bootm $loadaddr - $fdtaddr" 586 587 #define CONFIG_NFSBOOTCOMMAND \ 588 "setenv bootargs root=/dev/nfs rw " \ 589 "nfsroot=$serverip:$rootpath " \ 590 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 591 "console=$consoledev,$baudrate $othbootargs;" \ 592 "tftp $loadaddr $bootfile;" \ 593 "tftp $fdtaddr $fdtfile;" \ 594 "bootm $loadaddr - $fdtaddr" 595 596 #define CONFIG_RAMBOOTCOMMAND \ 597 "setenv bootargs root=/dev/ram rw " \ 598 "console=$consoledev,$baudrate $othbootargs;" \ 599 "tftp $ramdiskaddr $ramdiskfile;" \ 600 "tftp $loadaddr $bootfile;" \ 601 "tftp $fdtaddr $fdtfile;" \ 602 "bootm $loadaddr $ramdiskaddr $fdtaddr" 603 604 #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT 605 606 #endif /* __CONFIG_H */ 607