1 /* 2 * (C) Copyright 2013 3 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc 4 * 5 * based on P1022DS.h 6 * 7 * See file CREDITS for list of people who contributed to this 8 * project. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 23 * MA 02111-1307 USA 24 */ 25 26 #ifndef __CONFIG_H 27 #define __CONFIG_H 28 29 #ifdef CONFIG_SDCARD 30 #define CONFIG_RAMBOOT_SDCARD 31 #endif 32 33 #ifdef CONFIG_SPIFLASH 34 #define CONFIG_RAMBOOT_SPIFLASH 35 #endif 36 37 /* High Level Configuration Options */ 38 #define CONFIG_CONTROLCENTERD 39 #define CONFIG_MP /* support multiple processors */ 40 41 #define CONFIG_SYS_NO_FLASH 42 #define CONFIG_ENABLE_36BIT_PHYS 43 44 #ifdef CONFIG_PHYS_64BIT 45 #define CONFIG_ADDR_MAP 46 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ 47 #endif 48 49 #define CONFIG_L2_CACHE 50 #define CONFIG_BTB 51 52 #define CONFIG_SYS_CLK_FREQ 66666600 53 #define CONFIG_DDR_CLK_FREQ 66666600 54 55 #define CONFIG_SYS_RAMBOOT 56 57 #ifdef CONFIG_TRAILBLAZER 58 59 #define CONFIG_SYS_TEXT_BASE 0xf8fc0000 60 #define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc 61 #define CONFIG_SYS_MONITOR_LEN (256 * 1024) 62 63 /* 64 * Config the L2 Cache 65 */ 66 #define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000 67 #ifdef CONFIG_PHYS_64BIT 68 #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull 69 #else 70 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR 71 #endif 72 #define CONFIG_SYS_L2_SIZE (256 << 10) 73 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) 74 75 #else /* CONFIG_TRAILBLAZER */ 76 77 #define CONFIG_SYS_TEXT_BASE 0x11000000 78 #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc 79 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) 80 81 #endif /* CONFIG_TRAILBLAZER */ 82 83 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 84 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 85 86 /* 87 * Memory map 88 * 89 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable 90 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable 91 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable 92 * 93 * Localbus non-cacheable 94 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable 95 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable 96 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 97 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable 98 */ 99 100 #define CONFIG_SYS_INIT_RAM_LOCK 101 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ 102 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */ 103 #define CONFIG_SYS_GBL_DATA_OFFSET \ 104 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 105 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 106 107 #ifdef CONFIG_TRAILBLAZER 108 /* leave CCSRBAR at default, because u-boot expects it to be exactly there */ 109 #define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT 110 #else 111 #define CONFIG_SYS_CCSRBAR 0xffe00000 112 #endif 113 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR 114 #define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200) 115 116 /* 117 * DDR Setup 118 */ 119 120 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 121 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 122 #define CONFIG_SYS_SDRAM_SIZE 1024 123 #define CONFIG_VERY_BIG_RAM 124 125 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 126 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 127 128 #define CONFIG_SYS_MEMTEST_START 0x00000000 129 #define CONFIG_SYS_MEMTEST_END 0x3fffffff 130 131 #ifdef CONFIG_TRAILBLAZER 132 #define CONFIG_SPD_EEPROM 133 #define SPD_EEPROM_ADDRESS 0x52 134 /*#define CONFIG_FSL_DDR_INTERACTIVE*/ 135 #endif 136 137 /* 138 * Local Bus Definitions 139 */ 140 141 #define CONFIG_SYS_ELBC_BASE 0xe0000000 142 #ifdef CONFIG_PHYS_64BIT 143 #define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull 144 #else 145 #define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE 146 #endif 147 148 #define CONFIG_UART_BR_PRELIM \ 149 (BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V) 150 #define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7) 151 152 #define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */ 153 #define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */ 154 155 #define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM 156 #define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM 157 158 /* 159 * Serial Port 160 */ 161 #define CONFIG_CONS_INDEX 2 162 #define CONFIG_SYS_NS16550_SERIAL 163 #define CONFIG_SYS_NS16550_REG_SIZE 1 164 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 165 166 #define CONFIG_SYS_BAUDRATE_TABLE \ 167 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} 168 169 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) 170 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) 171 172 /* 173 * I2C 174 */ 175 #define CONFIG_SYS_I2C 176 #define CONFIG_SYS_I2C_FSL 177 #define CONFIG_SYS_FSL_I2C_SPEED 400000 178 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 179 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 180 #define CONFIG_SYS_FSL_I2C2_SPEED 400000 181 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F 182 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 183 184 #ifndef CONFIG_TRAILBLAZER 185 #endif 186 187 #define CONFIG_PCA9698 /* NXP PCA9698 */ 188 189 #define CONFIG_CMD_EEPROM 190 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 191 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 192 193 #ifndef CONFIG_TRAILBLAZER 194 /* 195 * eSPI - Enhanced SPI 196 */ 197 #define CONFIG_HARD_SPI 198 199 #define CONFIG_SF_DEFAULT_SPEED 10000000 200 #define CONFIG_SF_DEFAULT_MODE 0 201 #endif 202 203 #define CONFIG_SHA1 204 205 /* 206 * MMC 207 */ 208 #define CONFIG_GENERIC_MMC 209 210 #define CONFIG_FSL_ESDHC 211 #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR 212 213 #ifndef CONFIG_TRAILBLAZER 214 215 /* 216 * Video 217 */ 218 #define CONFIG_FSL_DIU_FB 219 #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000) 220 #define CONFIG_CMD_BMP 221 222 /* 223 * General PCI 224 * Memory space is mapped 1-1, but I/O space must start from 0. 225 */ 226 #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ 227 #define CONFIG_PCI_INDIRECT_BRIDGE 228 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 229 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ 230 #define CONFIG_CMD_PCI 231 232 #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ 233 #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ 234 235 #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 236 #ifdef CONFIG_PHYS_64BIT 237 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 238 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull 239 #else 240 #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 241 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000 242 #endif 243 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ 244 #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000 245 #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 246 #ifdef CONFIG_PHYS_64BIT 247 #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull 248 #else 249 #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 250 #endif 251 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ 252 253 /* 254 * SATA 255 */ 256 #define CONFIG_LIBATA 257 #define CONFIG_LBA48 258 #define CONFIG_CMD_SATA 259 260 #define CONFIG_FSL_SATA 261 #define CONFIG_SYS_SATA_MAX_DEVICE 2 262 #define CONFIG_SATA1 263 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR 264 #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA 265 #define CONFIG_SATA2 266 #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR 267 #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA 268 269 /* 270 * Ethernet 271 */ 272 #define CONFIG_TSEC_ENET 273 274 #define CONFIG_TSECV2 275 276 #define CONFIG_MII /* MII PHY management */ 277 #define CONFIG_TSEC1 1 278 #define CONFIG_TSEC1_NAME "eTSEC1" 279 #define CONFIG_TSEC2 1 280 #define CONFIG_TSEC2_NAME "eTSEC2" 281 282 #define TSEC1_PHY_ADDR 0 283 #define TSEC2_PHY_ADDR 1 284 285 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 286 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) 287 288 #define TSEC1_PHYIDX 0 289 #define TSEC2_PHYIDX 0 290 291 #define CONFIG_ETHPRIME "eTSEC1" 292 293 #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ 294 295 /* 296 * USB 297 */ 298 #define CONFIG_USB_EHCI 299 300 #define CONFIG_HAS_FSL_DR_USB 301 #define CONFIG_USB_EHCI_FSL 302 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 303 304 #endif /* CONFIG_TRAILBLAZER */ 305 306 /* 307 * Environment 308 */ 309 #if defined(CONFIG_TRAILBLAZER) 310 #define CONFIG_ENV_IS_NOWHERE 311 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 312 #elif defined(CONFIG_RAMBOOT_SPIFLASH) 313 #define CONFIG_ENV_IS_IN_SPI_FLASH 314 #define CONFIG_ENV_SPI_BUS 0 315 #define CONFIG_ENV_SPI_CS 0 316 #define CONFIG_ENV_SPI_MAX_HZ 10000000 317 #define CONFIG_ENV_SPI_MODE 0 318 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ 319 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ 320 #define CONFIG_ENV_SECT_SIZE 0x10000 321 #elif defined(CONFIG_RAMBOOT_SDCARD) 322 #define CONFIG_ENV_IS_IN_MMC 323 #define CONFIG_FSL_FIXED_MMC_LOCATION 324 #define CONFIG_ENV_SIZE 0x2000 325 #define CONFIG_SYS_MMC_ENV_DEV 0 326 #endif 327 328 #define CONFIG_SYS_EXTRA_ENV_RELOC 329 330 /* 331 * Command line configuration. 332 */ 333 #ifndef CONFIG_TRAILBLAZER 334 #define CONFIG_SYS_LONGHELP 335 #define CONFIG_CMDLINE_EDITING /* Command-line editing */ 336 #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ 337 #endif /* CONFIG_TRAILBLAZER */ 338 339 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ 340 #ifdef CONFIG_CMD_KGDB 341 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 342 #else 343 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 344 #endif 345 /* Print Buffer Size */ 346 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 347 #define CONFIG_SYS_MAXARGS 16 348 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 349 350 #ifndef CONFIG_TRAILBLAZER 351 352 #define CONFIG_CMD_ERRATA 353 #define CONFIG_CMD_IRQ 354 #define CONFIG_CMD_REGINFO 355 356 /* 357 * Board initialisation callbacks 358 */ 359 #define CONFIG_BOARD_EARLY_INIT_R 360 #define CONFIG_MISC_INIT_R 361 #define CONFIG_LAST_STAGE_INIT 362 363 #else /* CONFIG_TRAILBLAZER */ 364 365 #define CONFIG_BOARD_EARLY_INIT_R 366 #define CONFIG_LAST_STAGE_INIT 367 368 #endif /* CONFIG_TRAILBLAZER */ 369 370 /* 371 * Miscellaneous configurable options 372 */ 373 #define CONFIG_HW_WATCHDOG 374 #define CONFIG_LOADS_ECHO 375 #define CONFIG_SYS_LOADS_BAUD_CHANGE 376 #define CONFIG_DOS_PARTITION 377 378 /* 379 * For booting Linux, the board info and command line data 380 * have to be in the first 64 MB of memory, since this is 381 * the maximum mapped by the Linux kernel during initialization. 382 */ 383 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */ 384 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 385 386 /* 387 * Environment Configuration 388 */ 389 390 #ifdef CONFIG_TRAILBLAZER 391 392 #define CONFIG_BAUDRATE 115200 393 394 #define CONFIG_EXTRA_ENV_SETTINGS \ 395 "mp_holdoff=1\0" 396 397 #else 398 399 #define CONFIG_HOSTNAME controlcenterd 400 #define CONFIG_ROOTPATH "/opt/nfsroot" 401 #define CONFIG_BOOTFILE "uImage" 402 #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */ 403 404 #define CONFIG_LOADADDR 1000000 405 406 407 #define CONFIG_BAUDRATE 115200 408 409 #define CONFIG_EXTRA_ENV_SETTINGS \ 410 "netdev=eth0\0" \ 411 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ 412 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 413 "tftpflash=tftpboot $loadaddr $uboot && " \ 414 "protect off $ubootaddr +$filesize && " \ 415 "erase $ubootaddr +$filesize && " \ 416 "cp.b $loadaddr $ubootaddr $filesize && " \ 417 "protect on $ubootaddr +$filesize && " \ 418 "cmp.b $loadaddr $ubootaddr $filesize\0" \ 419 "consoledev=ttyS1\0" \ 420 "ramdiskaddr=2000000\0" \ 421 "ramdiskfile=rootfs.ext2.gz.uboot\0" \ 422 "fdtaddr=1e00000\0" \ 423 "fdtfile=controlcenterd.dtb\0" \ 424 "bdev=sda3\0" 425 426 /* these are used and NUL-terminated in env_default.h */ 427 #define CONFIG_NFSBOOTCOMMAND \ 428 "setenv bootargs root=/dev/nfs rw " \ 429 "nfsroot=$serverip:$rootpath " \ 430 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ 431 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 432 "tftp $loadaddr $bootfile;" \ 433 "tftp $fdtaddr $fdtfile;" \ 434 "bootm $loadaddr - $fdtaddr" 435 436 #define CONFIG_RAMBOOTCOMMAND \ 437 "setenv bootargs root=/dev/ram rw " \ 438 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \ 439 "tftp $ramdiskaddr $ramdiskfile;" \ 440 "tftp $loadaddr $bootfile;" \ 441 "tftp $fdtaddr $fdtfile;" \ 442 "bootm $loadaddr $ramdiskaddr $fdtaddr" 443 444 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND 445 446 #endif /* CONFIG_TRAILBLAZER */ 447 448 #endif 449