1ae440ab0SStefan Agner /* 2ae440ab0SStefan Agner * Copyright 2016 Toradex AG 3ae440ab0SStefan Agner * 4ae440ab0SStefan Agner * Configuration settings for the Colibri iMX7 module. 5ae440ab0SStefan Agner * 6ae440ab0SStefan Agner * based on mx7dsabresd.h: 7ae440ab0SStefan Agner * Copyright (C) 2015 Freescale Semiconductor, Inc. 8ae440ab0SStefan Agner * 9ae440ab0SStefan Agner * SPDX-License-Identifier: GPL-2.0+ 10ae440ab0SStefan Agner */ 11ae440ab0SStefan Agner 12ae440ab0SStefan Agner #ifndef __COLIBRI_IMX7_CONFIG_H 13ae440ab0SStefan Agner #define __COLIBRI_IMX7_CONFIG_H 14ae440ab0SStefan Agner 15ae440ab0SStefan Agner #include "mx7_common.h" 16ae440ab0SStefan Agner 17ae440ab0SStefan Agner /*#define CONFIG_DBG_MONITOR*/ 18ae440ab0SStefan Agner #define PHYS_SDRAM_SIZE SZ_512M 19ae440ab0SStefan Agner 20b891d010SMarcel Ziswiler #define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ 21b891d010SMarcel Ziswiler 22b891d010SMarcel Ziswiler #define CONFIG_ENV_VARS_UBOOT_CONFIG 23b891d010SMarcel Ziswiler #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 24ae440ab0SStefan Agner 25ae440ab0SStefan Agner /* Size of malloc() pool */ 26ae440ab0SStefan Agner #define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M) 27ae440ab0SStefan Agner 28ae440ab0SStefan Agner /* Network */ 29ae440ab0SStefan Agner #define CONFIG_FEC_MXC 30ae440ab0SStefan Agner #define CONFIG_MII 31ae440ab0SStefan Agner #define CONFIG_FEC_XCV_TYPE RMII 32ae440ab0SStefan Agner #define CONFIG_ETHPRIME "FEC" 33ae440ab0SStefan Agner #define CONFIG_FEC_MXC_PHYADDR 0 34ae440ab0SStefan Agner 35ae440ab0SStefan Agner #define CONFIG_IP_DEFRAG 36f7c81e28SMarcel Ziswiler #define CONFIG_TFTP_BLOCKSIZE 16352 37f7c81e28SMarcel Ziswiler #define CONFIG_TFTP_TSIZE 38ae440ab0SStefan Agner 39ae440ab0SStefan Agner /* ENET1 */ 40ae440ab0SStefan Agner #define IMX_FEC_BASE ENET_IPS_BASE_ADDR 41ae440ab0SStefan Agner 42ae440ab0SStefan Agner /* MMC Config*/ 43ae440ab0SStefan Agner #define CONFIG_SYS_FSL_ESDHC_ADDR 0 44ae440ab0SStefan Agner #define CONFIG_SYS_FSL_USDHC_NUM 1 45ae440ab0SStefan Agner 46ae440ab0SStefan Agner #undef CONFIG_BOOTM_PLAN9 47ae440ab0SStefan Agner #undef CONFIG_BOOTM_RTEMS 48ae440ab0SStefan Agner 49ae440ab0SStefan Agner /* I2C configs */ 50ae440ab0SStefan Agner #define CONFIG_SYS_I2C_MXC 51ae440ab0SStefan Agner #define CONFIG_SYS_I2C_SPEED 100000 52ae440ab0SStefan Agner 53ae440ab0SStefan Agner #define CONFIG_IPADDR 192.168.10.2 54ae440ab0SStefan Agner #define CONFIG_NETMASK 255.255.255.0 55ae440ab0SStefan Agner #define CONFIG_SERVERIP 192.168.10.1 56ae440ab0SStefan Agner 57ae440ab0SStefan Agner #define MEM_LAYOUT_ENV_SETTINGS \ 589af131e3SStefan Agner "bootm_size=0x10000000\0" \ 59ae440ab0SStefan Agner "fdt_addr_r=0x82000000\0" \ 60ae440ab0SStefan Agner "fdt_high=0xffffffff\0" \ 61ae440ab0SStefan Agner "initrd_high=0xffffffff\0" \ 62ae440ab0SStefan Agner "kernel_addr_r=0x81000000\0" \ 63ae440ab0SStefan Agner "ramdisk_addr_r=0x82100000\0" 64ae440ab0SStefan Agner 65ae440ab0SStefan Agner #define SD_BOOTCMD \ 66ae440ab0SStefan Agner "sdargs=root=/dev/mmcblk0p2 rw rootwait\0" \ 67ae440ab0SStefan Agner "sdboot=run setup; setenv bootargs ${defargs} ${sdargs} " \ 68ae440ab0SStefan Agner "${setupargs} ${vidargs}; echo Booting from MMC/SD card...; " \ 69ae440ab0SStefan Agner "run m4boot && " \ 70ae440ab0SStefan Agner "load mmc 0:1 ${kernel_addr_r} ${kernel_file} && " \ 71ae440ab0SStefan Agner "load mmc 0:1 ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ 72ae440ab0SStefan Agner "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ 73ae440ab0SStefan Agner 74ae440ab0SStefan Agner #define NFS_BOOTCMD \ 75ae440ab0SStefan Agner "nfsargs=ip=:::::eth0: root=/dev/nfs\0" \ 76ae440ab0SStefan Agner "nfsboot=run setup; " \ 77ae440ab0SStefan Agner "setenv bootargs ${defargs} ${nfsargs} " \ 78ae440ab0SStefan Agner "${setupargs} ${vidargs}; echo Booting from NFS...;" \ 79ae440ab0SStefan Agner "dhcp ${kernel_addr_r} && " \ 80ae440ab0SStefan Agner "tftp ${fdt_addr_r} ${soc}-colibri-${fdt_board}.dtb && " \ 81ae440ab0SStefan Agner "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ 82ae440ab0SStefan Agner 83ae440ab0SStefan Agner #define UBI_BOOTCMD \ 84ae440ab0SStefan Agner "ubiargs=ubi.mtd=ubi root=ubi0:rootfs rootfstype=ubifs " \ 85ae440ab0SStefan Agner "ubi.fm_autoconvert=1\0" \ 86ae440ab0SStefan Agner "ubiboot=run setup; " \ 87ae440ab0SStefan Agner "setenv bootargs ${defargs} ${ubiargs} " \ 88ae440ab0SStefan Agner "${setupargs} ${vidargs}; echo Booting from NAND...; " \ 89ae440ab0SStefan Agner "ubi part ubi && run m4boot && " \ 90ae440ab0SStefan Agner "ubi read ${kernel_addr_r} kernel && " \ 91ae440ab0SStefan Agner "ubi read ${fdt_addr_r} dtb && " \ 92ae440ab0SStefan Agner "run fdt_fixup && bootz ${kernel_addr_r} - ${fdt_addr_r}\0" \ 93ae440ab0SStefan Agner 94ae440ab0SStefan Agner #define CONFIG_BOOTCOMMAND "run ubiboot; run sdboot; run nfsboot" 95ae440ab0SStefan Agner 96ae440ab0SStefan Agner #define CONFIG_EXTRA_ENV_SETTINGS \ 97ae440ab0SStefan Agner MEM_LAYOUT_ENV_SETTINGS \ 98ae440ab0SStefan Agner NFS_BOOTCMD \ 99ae440ab0SStefan Agner SD_BOOTCMD \ 100ae440ab0SStefan Agner UBI_BOOTCMD \ 101ae440ab0SStefan Agner "console=ttymxc0\0" \ 102ae440ab0SStefan Agner "defargs=\0" \ 103ae440ab0SStefan Agner "fdt_board=eval-v3\0" \ 104ae440ab0SStefan Agner "fdt_fixup=;\0" \ 105ae440ab0SStefan Agner "m4boot=;\0" \ 106ae440ab0SStefan Agner "ip_dyn=yes\0" \ 107ae440ab0SStefan Agner "kernel_file=zImage\0" \ 108ae440ab0SStefan Agner "mtdparts=" MTDPARTS_DEFAULT "\0" \ 109ae440ab0SStefan Agner "setethupdate=if env exists ethaddr; then; else setenv ethaddr " \ 110ae440ab0SStefan Agner "00:14:2d:00:00:00; fi; tftpboot ${loadaddr} " \ 111ae440ab0SStefan Agner "${board}/flash_eth.img && source ${loadaddr}\0" \ 112ae440ab0SStefan Agner "setsdupdate=mmc rescan && setenv interface mmc && " \ 113ae440ab0SStefan Agner "fatload ${interface} 0:1 ${loadaddr} " \ 114ae440ab0SStefan Agner "${board}/flash_blk.img && source ${loadaddr}\0" \ 115ae440ab0SStefan Agner "setup=setenv setupargs " \ 116ae440ab0SStefan Agner "console=tty1 console=${console}" \ 11764095704SStefan Agner ",${baudrate}n8 ${memargs} consoleblank=0\0" \ 118ae440ab0SStefan Agner "setupdate=run setsdupdate || run setusbupdate || run setethupdate\0" \ 119ae440ab0SStefan Agner "setusbupdate=usb start && setenv interface usb && " \ 120ae440ab0SStefan Agner "fatload ${interface} 0:1 ${loadaddr} " \ 121ae440ab0SStefan Agner "${board}/flash_blk.img && source ${loadaddr}\0" \ 122ae440ab0SStefan Agner "splashpos=m,m\0" \ 123ae440ab0SStefan Agner "videomode=video=ctfb:x:640,y:480,depth:18,pclk:39722,le:48,ri:16,up:33,lo:10,hs:96,vs:2,sync:0,vmode:0\0" \ 124*38045f54SStefan Agner "updlevel=2\0" 125ae440ab0SStefan Agner 126ae440ab0SStefan Agner /* Miscellaneous configurable options */ 127ae440ab0SStefan Agner #define CONFIG_SYS_LONGHELP 128ae440ab0SStefan Agner 129ae440ab0SStefan Agner #define CONFIG_SYS_MEMTEST_START 0x80000000 130ae440ab0SStefan Agner #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x0c000000) 131ae440ab0SStefan Agner 132ae440ab0SStefan Agner #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 133ae440ab0SStefan Agner #define CONFIG_SYS_HZ 1000 134ae440ab0SStefan Agner 135ae440ab0SStefan Agner /* Physical Memory Map */ 136ae440ab0SStefan Agner #define CONFIG_NR_DRAM_BANKS 1 137ae440ab0SStefan Agner #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 138ae440ab0SStefan Agner 139ae440ab0SStefan Agner #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 140ae440ab0SStefan Agner #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 141ae440ab0SStefan Agner #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 142ae440ab0SStefan Agner 143ae440ab0SStefan Agner #define CONFIG_SYS_INIT_SP_OFFSET \ 144ae440ab0SStefan Agner (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 145ae440ab0SStefan Agner #define CONFIG_SYS_INIT_SP_ADDR \ 146ae440ab0SStefan Agner (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 147ae440ab0SStefan Agner 148e856bdcfSMasahiro Yamada /* environment organization */ 149ae440ab0SStefan Agner 150ae440ab0SStefan Agner #if defined(CONFIG_ENV_IS_IN_MMC) 151ae440ab0SStefan Agner #define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ 152ae440ab0SStefan Agner #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ 153ae440ab0SStefan Agner #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ 154ae440ab0SStefan Agner #define CONFIG_ENV_OFFSET (8 * SZ_64K) 155ae440ab0SStefan Agner #elif defined(CONFIG_ENV_IS_IN_NAND) 156ae440ab0SStefan Agner #define CONFIG_ENV_SECT_SIZE (128 * 1024) 157*38045f54SStefan Agner #define CONFIG_ENV_OFFSET (28 * CONFIG_ENV_SECT_SIZE) 158ae440ab0SStefan Agner #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE 159ae440ab0SStefan Agner #endif 160ae440ab0SStefan Agner 161ae440ab0SStefan Agner /* NAND stuff */ 162ae440ab0SStefan Agner #define CONFIG_SYS_MAX_NAND_DEVICE 1 163ae440ab0SStefan Agner #define CONFIG_SYS_NAND_BASE 0x40000000 164ae440ab0SStefan Agner #define CONFIG_SYS_NAND_5_ADDR_CYCLE 165ae440ab0SStefan Agner #define CONFIG_SYS_NAND_ONFI_DETECTION 166ae440ab0SStefan Agner #define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES 167ae440ab0SStefan Agner 168ae440ab0SStefan Agner /* Dynamic MTD partition support */ 169ae440ab0SStefan Agner 170ae440ab0SStefan Agner /* DMA stuff, needed for GPMI/MXS NAND support */ 171ae440ab0SStefan Agner 172ae440ab0SStefan Agner /* USB Configs */ 173ae440ab0SStefan Agner #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 174ae440ab0SStefan Agner 175ae440ab0SStefan Agner #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 176ae440ab0SStefan Agner #define CONFIG_MXC_USB_FLAGS 0 177ae440ab0SStefan Agner #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 178ae440ab0SStefan Agner 179ae440ab0SStefan Agner #define CONFIG_IMX_THERMAL 180ae440ab0SStefan Agner 181ae440ab0SStefan Agner #define CONFIG_USBD_HS 182ae440ab0SStefan Agner 183ae440ab0SStefan Agner #define CONFIG_USB_FUNCTION_MASS_STORAGE 184ae440ab0SStefan Agner 185ae440ab0SStefan Agner /* USB Device Firmware Update support */ 186ae440ab0SStefan Agner #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M 187ae440ab0SStefan Agner #define DFU_DEFAULT_POLL_TIMEOUT 300 188ae440ab0SStefan Agner 189ae440ab0SStefan Agner #ifdef CONFIG_VIDEO 190ae440ab0SStefan Agner #define CONFIG_VIDEO_MXS 191ae440ab0SStefan Agner #define CONFIG_VIDEO_LOGO 192ae440ab0SStefan Agner #define CONFIG_SPLASH_SCREEN 193ae440ab0SStefan Agner #define CONFIG_SPLASH_SCREEN_ALIGN 194ae440ab0SStefan Agner #define CONFIG_BMP_16BPP 195ae440ab0SStefan Agner #define CONFIG_VIDEO_BMP_RLE8 196ae440ab0SStefan Agner #define CONFIG_VIDEO_BMP_LOGO 197ae440ab0SStefan Agner #endif 198ae440ab0SStefan Agner 199ae440ab0SStefan Agner #endif 200