1 /* 2 * cm_t43.h 3 * 4 * Copyright (C) 2015 Compulab, Ltd. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_CM_T43_H 10 #define __CONFIG_CM_T43_H 11 12 #define CONFIG_AM43XX 13 #define CONFIG_CM_T43 14 #define CONFIG_ARCH_CPU_INIT 15 #define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2GB */ 16 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ 17 18 #include <asm/arch/omap.h> 19 20 /* Serial support */ 21 #define CONFIG_DM_SERIAL 22 #define CONFIG_SYS_NS16550 23 #define CONFIG_SYS_NS16550_SERIAL 24 #define CONFIG_SYS_NS16550_CLK 48000000 25 #define CONFIG_SYS_NS16550_COM1 0x44e09000 26 27 /* NAND support */ 28 #define CONFIG_NAND 29 #define CONFIG_NAND_OMAP_ELM 30 #define CONFIG_SYS_NAND_ONFI_DETECTION 31 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 32 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 33 #define CONFIG_SYS_NAND_OOBSIZE 64 34 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 35 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 36 #define CONFIG_SYS_NAND_ECCSIZE 512 37 #define CONFIG_SYS_NAND_ECCBYTES 14 38 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 39 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 40 CONFIG_SYS_NAND_PAGE_SIZE) 41 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 42 10, 11, 12, 13, 14, 15, 16, 17, \ 43 18, 19, 20, 21, 22, 23, 24, 25, \ 44 26, 27, 28, 29, 30, 31, 32, 33, \ 45 34, 35, 36, 37, 38, 39, 40, 41, \ 46 42, 43, 44, 45, 46, 47, 48, 49, \ 47 50, 51, 52, 53, 54, 55, 56, 57, } 48 49 /* CPSW Ethernet support */ 50 #define CONFIG_DRIVER_TI_CPSW 51 #define CONFIG_MII 52 #define CONFIG_BOOTP_DEFAULT 53 #define CONFIG_BOOTP_SEND_HOSTNAME 54 #define CONFIG_BOOTP_GATEWAY 55 #define CONFIG_NET_MULTI 56 #define CONFIG_PHY_GIGE 57 #define CONFIG_PHY_ATHEROS 58 #define CONFIG_PHYLIB 59 #define CONFIG_SYS_RX_ETH_BUFFER 64 60 61 /* USB support */ 62 #define CONFIG_USB_HOST 63 #define CONFIG_USB_XHCI 64 #define CONFIG_USB_XHCI_OMAP 65 #define CONFIG_USB_XHCI_DWC3 66 #define CONFIG_USB_STORAGE 67 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 68 #define CONFIG_OMAP_USB_PHY 69 #define CONFIG_AM437X_USB2PHY2_HOST 70 71 /* SPI Flash support */ 72 #define CONFIG_SPI_FLASH 73 #define CONFIG_SPI_FLASH_MACRONIX 74 #define CONFIG_SPI_FLASH_ATMEL 75 #define CONFIG_SPI_FLASH_EON 76 #define CONFIG_SPI_FLASH_GIGADEVICE 77 #define CONFIG_SPI_FLASH_SPANSION 78 #define CONFIG_SPI_FLASH_STMICRO 79 #define CONFIG_SPI_FLASH_SST 80 #define CONFIG_SPI_FLASH_WINBOND 81 #define CONFIG_TI_SPI_MMAP 82 #define CONFIG_SPI_FLASH_BAR 83 #define CONFIG_SF_DEFAULT_SPEED 48000000 84 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 85 86 /* Power */ 87 #define CONFIG_POWER 88 #define CONFIG_POWER_I2C 89 #define CONFIG_POWER_TPS65218 90 91 /* Enabling L2 Cache */ 92 #define CONFIG_SYS_L2_PL310 93 #define CONFIG_SYS_PL310_BASE 0x48242000 94 #define CONFIG_SYS_CACHELINE_SIZE 32 95 96 /* 97 * Since SPL did pll and ddr initialization for us, 98 * we don't need to do it twice. 99 */ 100 #if !defined(CONFIG_SPL_BUILD) 101 #define CONFIG_SKIP_LOWLEVEL_INIT 102 #endif 103 104 #define CONFIG_HSMMC2_8BIT 105 106 #include <configs/ti_armv7_omap.h> 107 #undef CONFIG_SPL_OS_BOOT 108 #undef CONFIG_SPL_GPIO_SUPPORT 109 #undef CONFIG_SPL_NAND_SUPPORT 110 #undef CONFIG_SPL_BOARD_INIT 111 #undef CONFIG_BOOTDELAY 112 #include <config_distro_defaults.h> 113 #define CONFIG_ZERO_BOOTDELAY_CHECK 114 #undef CONFIG_CMD_IMLS 115 116 #define CONFIG_ENV_SIZE (16 * 1024) 117 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 118 119 #define V_OSCK 24000000 /* Clock output from T2 */ 120 #define V_SCLK (V_OSCK) 121 122 #define CONFIG_ENV_IS_IN_SPI_FLASH 123 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 124 #define CONFIG_ENV_OFFSET (768 * 1024) 125 #define CONFIG_ENV_SPI_MAX_HZ 48000000 126 127 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" 128 129 /* Enhance our eMMC support / experience. */ 130 #define CONFIG_CMD_GPT 131 #define CONFIG_EFI_PARTITION 132 133 #define CONFIG_EXTRA_ENV_SETTINGS \ 134 "loadaddr=0x80200000\0" \ 135 "fdtaddr=0x81200000\0" \ 136 "bootm_size=0x8000000\0" \ 137 "autoload=no\0" \ 138 "console=ttyO0,115200n8\0" \ 139 "fdtfile=am437x-sb-som-t43.dtb\0" \ 140 "kernel=zImage-cm-t43\0" \ 141 "bootscr=bootscr.img\0" \ 142 "emmcroot=/dev/mmcblk0p2 rw\0" \ 143 "emmcrootfstype=ext4 rootwait\0" \ 144 "emmcargs=setenv bootargs console=${console} " \ 145 "root=${emmcroot} " \ 146 "rootfstype=${emmcrootfstype}\0" \ 147 "loadbootscript=load mmc 0 ${loadaddr} ${bootscr}\0" \ 148 "bootscript=echo Running bootscript from mmc ...; " \ 149 "source ${loadaddr}\0" \ 150 "emmcboot=echo Booting from emmc ... && " \ 151 "run emmcargs && " \ 152 "load mmc 1 ${loadaddr} ${kernel} && " \ 153 "load mmc 1 ${fdtaddr} ${fdtfile} && " \ 154 "bootz ${loadaddr} - ${fdtaddr}\0" 155 156 #define CONFIG_BOOTCOMMAND \ 157 "mmc dev 0; " \ 158 "if mmc rescan; then " \ 159 "if run loadbootscript; then " \ 160 "run bootscript; " \ 161 "fi; " \ 162 "fi; " \ 163 "mmc dev 1; " \ 164 "if mmc rescan; then " \ 165 "run emmcboot; " \ 166 "fi;" 167 168 169 #define CONFIG_CONS_INDEX 1 170 171 /* SPL defines. */ 172 #define CONFIG_SPL_TEXT_BASE 0x40300350 173 #define CONFIG_SPL_MAX_SIZE (64 * 1024) 174 #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + (128 << 20)) 175 #define CONFIG_SPL_POWER_SUPPORT 176 #define CONFIG_SYS_SPI_U_BOOT_OFFS (256 * 1024) 177 #define CONFIG_SPL_SPI_SUPPORT 178 #define CONFIG_SPL_SPI_FLASH_SUPPORT 179 #define CONFIG_SPL_SPI_LOAD 180 181 #endif /* __CONFIG_CM_T43_H */ 182