1 /* 2 * (C) Copyright 2013 CompuLab, Ltd. 3 * Author: Igor Grinberg <grinberg@compulab.co.il> 4 * 5 * Configuration settings for the CompuLab CM-T3517 board 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 /* 14 * High Level Configuration Options 15 */ 16 #define CONFIG_OMAP /* in a TI OMAP core */ 17 #define CONFIG_CM_T3517 /* working with CM-T3517 */ 18 #define CONFIG_OMAP_COMMON 19 #define CONFIG_SYS_GENERIC_BOARD 20 21 #define CONFIG_SYS_TEXT_BASE 0x80008000 22 23 /* 24 * This is needed for the DMA stuff. 25 * Although the default iss 64, we still define it 26 * to be on the safe side once the default is changed. 27 */ 28 #define CONFIG_SYS_CACHELINE_SIZE 64 29 30 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 31 32 #include <asm/arch/cpu.h> /* get chip and board defs */ 33 #include <asm/arch/omap3.h> 34 35 /* 36 * Display CPU and Board information 37 */ 38 #define CONFIG_DISPLAY_CPUINFO 39 #define CONFIG_DISPLAY_BOARDINFO 40 41 /* Clock Defines */ 42 #define V_OSCK 26000000 /* Clock output from T2 */ 43 #define V_SCLK (V_OSCK >> 1) 44 45 #define CONFIG_MISC_INIT_R 46 47 #define CONFIG_OF_LIBFDT 48 /* 49 * The early kernel mapping on ARM currently only maps from the base of DRAM 50 * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. 51 * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, 52 * so that leaves DRAM base to DRAM base + 0x4000 available. 53 */ 54 #define CONFIG_SYS_BOOTMAPSZ 0x4000 55 56 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 57 #define CONFIG_SETUP_MEMORY_TAGS 58 #define CONFIG_INITRD_TAG 59 #define CONFIG_REVISION_TAG 60 #define CONFIG_SERIAL_TAG 61 62 /* 63 * Size of malloc() pool 64 */ 65 #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ 66 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 67 68 /* 69 * Hardware drivers 70 */ 71 72 /* 73 * NS16550 Configuration 74 */ 75 #define CONFIG_SYS_NS16550 76 #define CONFIG_SYS_NS16550_SERIAL 77 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 78 #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 79 80 /* 81 * select serial console configuration 82 */ 83 #define CONFIG_CONS_INDEX 3 84 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 85 #define CONFIG_SERIAL3 3 /* UART3 */ 86 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 87 88 /* allow to overwrite serial and ethaddr */ 89 #define CONFIG_ENV_OVERWRITE 90 #define CONFIG_BAUDRATE 115200 91 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 92 115200} 93 94 #define CONFIG_OMAP_GPIO 95 96 #define CONFIG_GENERIC_MMC 97 #define CONFIG_MMC 98 #define CONFIG_OMAP_HSMMC 99 #define CONFIG_DOS_PARTITION 100 101 /* commands to include */ 102 #include <config_cmd_default.h> 103 104 #define CONFIG_CMD_CACHE 105 #define CONFIG_CMD_EXT2 /* EXT2 Support */ 106 #define CONFIG_CMD_FAT /* FAT support */ 107 #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */ 108 #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 109 #define CONFIG_MTD_PARTITIONS 110 #define MTDIDS_DEFAULT "nand0=nand" 111 #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\ 112 "1920k(u-boot),256k(u-boot-env),"\ 113 "4m(kernel),-(fs)" 114 115 #define CONFIG_CMD_I2C /* I2C serial bus support */ 116 #define CONFIG_CMD_MMC /* MMC support */ 117 #define CONFIG_CMD_NAND /* NAND support */ 118 #define CONFIG_CMD_GPIO 119 120 #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ 121 #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ 122 #undef CONFIG_CMD_IMLS /* List all found images */ 123 124 #define CONFIG_SYS_NO_FLASH 125 #define CONFIG_SYS_I2C 126 #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 127 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 128 #define CONFIG_SYS_I2C_OMAP34XX 129 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 130 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 131 #define CONFIG_SYS_I2C_EEPROM_BUS 0 132 #define CONFIG_I2C_MULTI_BUS 133 134 /* 135 * Board NAND Info. 136 */ 137 #define CONFIG_SYS_NAND_QUIET_TEST 138 #define CONFIG_NAND_OMAP_GPMC 139 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 140 /* to access nand */ 141 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 142 /* to access nand at */ 143 /* CS0 */ 144 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 145 /* devices */ 146 147 /* Environment information */ 148 #define CONFIG_BOOTDELAY 3 149 #define CONFIG_ZERO_BOOTDELAY_CHECK 150 151 #define CONFIG_EXTRA_ENV_SETTINGS \ 152 "loadaddr=0x82000000\0" \ 153 "baudrate=115200\0" \ 154 "console=ttyO2,115200n8\0" \ 155 "mpurate=auto\0" \ 156 "vram=12M\0" \ 157 "dvimode=1024x768MR-16@60\0" \ 158 "defaultdisplay=dvi\0" \ 159 "mmcdev=0\0" \ 160 "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ 161 "mmcrootfstype=ext4\0" \ 162 "nandroot=/dev/mtdblock4 rw\0" \ 163 "nandrootfstype=ubifs\0" \ 164 "mmcargs=setenv bootargs console=${console} " \ 165 "mpurate=${mpurate} " \ 166 "vram=${vram} " \ 167 "omapfb.mode=dvi:${dvimode} " \ 168 "omapdss.def_disp=${defaultdisplay} " \ 169 "root=${mmcroot} " \ 170 "rootfstype=${mmcrootfstype}\0" \ 171 "nandargs=setenv bootargs console=${console} " \ 172 "mpurate=${mpurate} " \ 173 "vram=${vram} " \ 174 "omapfb.mode=dvi:${dvimode} " \ 175 "omapdss.def_disp=${defaultdisplay} " \ 176 "root=${nandroot} " \ 177 "rootfstype=${nandrootfstype}\0" \ 178 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 179 "bootscript=echo Running bootscript from mmc ...; " \ 180 "source ${loadaddr}\0" \ 181 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 182 "mmcboot=echo Booting from mmc ...; " \ 183 "run mmcargs; " \ 184 "bootm ${loadaddr}\0" \ 185 "nandboot=echo Booting from nand ...; " \ 186 "run nandargs; " \ 187 "nand read ${loadaddr} 2a0000 400000; " \ 188 "bootm ${loadaddr}\0" \ 189 190 #define CONFIG_CMD_BOOTZ 191 #define CONFIG_BOOTCOMMAND \ 192 "mmc dev ${mmcdev}; if mmc rescan; then " \ 193 "if run loadbootscript; then " \ 194 "run bootscript; " \ 195 "else " \ 196 "if run loaduimage; then " \ 197 "run mmcboot; " \ 198 "else run nandboot; " \ 199 "fi; " \ 200 "fi; " \ 201 "else run nandboot; fi" 202 203 /* 204 * Miscellaneous configurable options 205 */ 206 #define CONFIG_AUTO_COMPLETE 207 #define CONFIG_CMDLINE_EDITING 208 #define CONFIG_TIMESTAMP 209 #define CONFIG_SYS_AUTOLOAD "no" 210 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 211 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 212 #define CONFIG_SYS_PROMPT "CM-T3517 # " 213 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 214 /* Print Buffer Size */ 215 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 216 sizeof(CONFIG_SYS_PROMPT) + 16) 217 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 218 /* Boot Argument Buffer Size */ 219 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 220 221 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 222 223 /* 224 * AM3517 has 12 GP timers, they can be driven by the system clock 225 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 226 * This rate is divided by a local divisor. 227 */ 228 #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 229 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 230 #define CONFIG_SYS_HZ 1000 231 232 /*----------------------------------------------------------------------- 233 * Physical Memory Map 234 */ 235 #define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */ 236 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 237 #define CONFIG_SYS_CS0_SIZE (256 << 20) 238 239 /*----------------------------------------------------------------------- 240 * FLASH and environment organization 241 */ 242 243 /* **** PISMO SUPPORT *** */ 244 /* Monitor at start of flash */ 245 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 246 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 247 248 #define CONFIG_ENV_IS_IN_NAND 249 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 250 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 251 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 252 253 /* additions for new relocation code, must be added to all boards */ 254 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 255 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 256 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 257 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 258 CONFIG_SYS_INIT_RAM_SIZE - \ 259 GENERATED_GBL_DATA_SIZE) 260 261 /* Status LED */ 262 #define CONFIG_STATUS_LED /* Status LED enabled */ 263 #define CONFIG_BOARD_SPECIFIC_LED 264 #define CONFIG_GPIO_LED 265 #define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ 266 #define GREEN_LED_DEV 0 267 #define STATUS_LED_BIT GREEN_LED_GPIO 268 #define STATUS_LED_STATE STATUS_LED_ON 269 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) 270 #define STATUS_LED_BOOT GREEN_LED_DEV 271 272 /* GPIO banks */ 273 #ifdef CONFIG_STATUS_LED 274 #define CONFIG_OMAP3_GPIO_6 /* GPIO186 is in GPIO bank 6 */ 275 #endif 276 277 #endif /* __CONFIG_H */ 278