1b09bf723SIgor Grinberg /* 2b09bf723SIgor Grinberg * (C) Copyright 2013 CompuLab, Ltd. 3b09bf723SIgor Grinberg * Author: Igor Grinberg <grinberg@compulab.co.il> 4b09bf723SIgor Grinberg * 5b09bf723SIgor Grinberg * Configuration settings for the CompuLab CM-T3517 board 6b09bf723SIgor Grinberg * 7b09bf723SIgor Grinberg * SPDX-License-Identifier: GPL-2.0+ 8b09bf723SIgor Grinberg */ 9b09bf723SIgor Grinberg 10b09bf723SIgor Grinberg #ifndef __CONFIG_H 11b09bf723SIgor Grinberg #define __CONFIG_H 12b09bf723SIgor Grinberg 13b09bf723SIgor Grinberg /* 14b09bf723SIgor Grinberg * High Level Configuration Options 15b09bf723SIgor Grinberg */ 16b09bf723SIgor Grinberg #define CONFIG_CM_T3517 /* working with CM-T3517 */ 17b09bf723SIgor Grinberg 18b09bf723SIgor Grinberg #define CONFIG_SYS_TEXT_BASE 0x80008000 19b09bf723SIgor Grinberg 20b09bf723SIgor Grinberg /* 21b09bf723SIgor Grinberg * This is needed for the DMA stuff. 22b09bf723SIgor Grinberg * Although the default iss 64, we still define it 23b09bf723SIgor Grinberg * to be on the safe side once the default is changed. 24b09bf723SIgor Grinberg */ 25b09bf723SIgor Grinberg 26b09bf723SIgor Grinberg #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 27b09bf723SIgor Grinberg 28b09bf723SIgor Grinberg #include <asm/arch/cpu.h> /* get chip and board defs */ 29987ec585SNishanth Menon #include <asm/arch/omap.h> 30b09bf723SIgor Grinberg 31f3b44e8bSDmitry Lifshitz #define CONFIG_MACH_TYPE MACH_TYPE_CM_T3517 32f3b44e8bSDmitry Lifshitz 33b09bf723SIgor Grinberg /* Clock Defines */ 34b09bf723SIgor Grinberg #define V_OSCK 26000000 /* Clock output from T2 */ 35b09bf723SIgor Grinberg #define V_SCLK (V_OSCK >> 1) 36b09bf723SIgor Grinberg 37b09bf723SIgor Grinberg #define CONFIG_MISC_INIT_R 38b09bf723SIgor Grinberg 39b09bf723SIgor Grinberg /* 40b09bf723SIgor Grinberg * The early kernel mapping on ARM currently only maps from the base of DRAM 41b09bf723SIgor Grinberg * to the end of the kernel image. The kernel is loaded at DRAM base + 0x8000. 42b09bf723SIgor Grinberg * The early kernel pagetable uses DRAM base + 0x4000 to DRAM base + 0x8000, 43b09bf723SIgor Grinberg * so that leaves DRAM base to DRAM base + 0x4000 available. 44b09bf723SIgor Grinberg */ 45b09bf723SIgor Grinberg #define CONFIG_SYS_BOOTMAPSZ 0x4000 46b09bf723SIgor Grinberg 47b09bf723SIgor Grinberg #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 48b09bf723SIgor Grinberg #define CONFIG_SETUP_MEMORY_TAGS 49b09bf723SIgor Grinberg #define CONFIG_INITRD_TAG 50b09bf723SIgor Grinberg #define CONFIG_REVISION_TAG 51b09bf723SIgor Grinberg #define CONFIG_SERIAL_TAG 52b09bf723SIgor Grinberg 53b09bf723SIgor Grinberg /* 54b09bf723SIgor Grinberg * Size of malloc() pool 55b09bf723SIgor Grinberg */ 562f6e4bf8SDmitry Lifshitz #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ 57b09bf723SIgor Grinberg #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 58b09bf723SIgor Grinberg 59b09bf723SIgor Grinberg /* 60b09bf723SIgor Grinberg * Hardware drivers 61b09bf723SIgor Grinberg */ 62b09bf723SIgor Grinberg 63b09bf723SIgor Grinberg /* 64b09bf723SIgor Grinberg * NS16550 Configuration 65b09bf723SIgor Grinberg */ 66b09bf723SIgor Grinberg #define CONFIG_SYS_NS16550_SERIAL 67b09bf723SIgor Grinberg #define CONFIG_SYS_NS16550_REG_SIZE (-4) 68b09bf723SIgor Grinberg #define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 69b09bf723SIgor Grinberg 70b09bf723SIgor Grinberg /* 71b09bf723SIgor Grinberg * select serial console configuration 72b09bf723SIgor Grinberg */ 73b09bf723SIgor Grinberg #define CONFIG_CONS_INDEX 3 74b09bf723SIgor Grinberg #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 75b09bf723SIgor Grinberg #define CONFIG_SERIAL3 3 /* UART3 */ 76b09bf723SIgor Grinberg 77b09bf723SIgor Grinberg /* allow to overwrite serial and ethaddr */ 78b09bf723SIgor Grinberg #define CONFIG_ENV_OVERWRITE 79b09bf723SIgor Grinberg #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 80b09bf723SIgor Grinberg 115200} 81b09bf723SIgor Grinberg 82011f5c13SIgor Grinberg /* USB */ 83011f5c13SIgor Grinberg #define CONFIG_USB_MUSB_AM35X 84011f5c13SIgor Grinberg 85011f5c13SIgor Grinberg #ifndef CONFIG_USB_MUSB_AM35X 86011f5c13SIgor Grinberg #define CONFIG_USB_OMAP3 87011f5c13SIgor Grinberg #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 146 88011f5c13SIgor Grinberg #define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 147 89011f5c13SIgor Grinberg #else /* !CONFIG_USB_MUSB_AM35X */ 9095de1e2fSPaul Kocialkowski #define CONFIG_USB_MUSB_PIO_ONLY 91011f5c13SIgor Grinberg #endif /* CONFIG_USB_MUSB_AM35X */ 92011f5c13SIgor Grinberg 93b09bf723SIgor Grinberg /* commands to include */ 94b09bf723SIgor Grinberg 95b09bf723SIgor Grinberg #define CONFIG_SYS_I2C 96b09bf723SIgor Grinberg #define CONFIG_SYS_OMAP24_I2C_SPEED 400000 97b09bf723SIgor Grinberg #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 98b09bf723SIgor Grinberg #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 99b09bf723SIgor Grinberg #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 100b09bf723SIgor Grinberg #define CONFIG_SYS_I2C_EEPROM_BUS 0 101b09bf723SIgor Grinberg #define CONFIG_I2C_MULTI_BUS 102b09bf723SIgor Grinberg 103b09bf723SIgor Grinberg /* 104b09bf723SIgor Grinberg * Board NAND Info. 105b09bf723SIgor Grinberg */ 106b09bf723SIgor Grinberg #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 107b09bf723SIgor Grinberg /* to access nand */ 108b09bf723SIgor Grinberg #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 109b09bf723SIgor Grinberg /* to access nand at */ 110b09bf723SIgor Grinberg /* CS0 */ 111b09bf723SIgor Grinberg #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ 112b09bf723SIgor Grinberg /* devices */ 113b09bf723SIgor Grinberg 114b09bf723SIgor Grinberg /* Environment information */ 115b09bf723SIgor Grinberg #define CONFIG_EXTRA_ENV_SETTINGS \ 116b09bf723SIgor Grinberg "loadaddr=0x82000000\0" \ 117b09bf723SIgor Grinberg "baudrate=115200\0" \ 118b09bf723SIgor Grinberg "console=ttyO2,115200n8\0" \ 119e093d0b2SDmitry Lifshitz "netretry=yes\0" \ 120b09bf723SIgor Grinberg "mpurate=auto\0" \ 121b09bf723SIgor Grinberg "vram=12M\0" \ 122b09bf723SIgor Grinberg "dvimode=1024x768MR-16@60\0" \ 123b09bf723SIgor Grinberg "defaultdisplay=dvi\0" \ 124b09bf723SIgor Grinberg "mmcdev=0\0" \ 125b09bf723SIgor Grinberg "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ 126b09bf723SIgor Grinberg "mmcrootfstype=ext4\0" \ 127b09bf723SIgor Grinberg "nandroot=/dev/mtdblock4 rw\0" \ 128b09bf723SIgor Grinberg "nandrootfstype=ubifs\0" \ 129b09bf723SIgor Grinberg "mmcargs=setenv bootargs console=${console} " \ 130b09bf723SIgor Grinberg "mpurate=${mpurate} " \ 131b09bf723SIgor Grinberg "vram=${vram} " \ 132b09bf723SIgor Grinberg "omapfb.mode=dvi:${dvimode} " \ 133b09bf723SIgor Grinberg "omapdss.def_disp=${defaultdisplay} " \ 134b09bf723SIgor Grinberg "root=${mmcroot} " \ 135b09bf723SIgor Grinberg "rootfstype=${mmcrootfstype}\0" \ 136b09bf723SIgor Grinberg "nandargs=setenv bootargs console=${console} " \ 137b09bf723SIgor Grinberg "mpurate=${mpurate} " \ 138b09bf723SIgor Grinberg "vram=${vram} " \ 139b09bf723SIgor Grinberg "omapfb.mode=dvi:${dvimode} " \ 140b09bf723SIgor Grinberg "omapdss.def_disp=${defaultdisplay} " \ 141b09bf723SIgor Grinberg "root=${nandroot} " \ 142b09bf723SIgor Grinberg "rootfstype=${nandrootfstype}\0" \ 143b09bf723SIgor Grinberg "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 144b09bf723SIgor Grinberg "bootscript=echo Running bootscript from mmc ...; " \ 145b09bf723SIgor Grinberg "source ${loadaddr}\0" \ 146b09bf723SIgor Grinberg "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 147b09bf723SIgor Grinberg "mmcboot=echo Booting from mmc ...; " \ 148b09bf723SIgor Grinberg "run mmcargs; " \ 149b09bf723SIgor Grinberg "bootm ${loadaddr}\0" \ 150b09bf723SIgor Grinberg "nandboot=echo Booting from nand ...; " \ 151b09bf723SIgor Grinberg "run nandargs; " \ 152b09bf723SIgor Grinberg "nand read ${loadaddr} 2a0000 400000; " \ 153b09bf723SIgor Grinberg "bootm ${loadaddr}\0" \ 154b09bf723SIgor Grinberg 155b09bf723SIgor Grinberg #define CONFIG_BOOTCOMMAND \ 156b09bf723SIgor Grinberg "mmc dev ${mmcdev}; if mmc rescan; then " \ 157b09bf723SIgor Grinberg "if run loadbootscript; then " \ 158b09bf723SIgor Grinberg "run bootscript; " \ 159b09bf723SIgor Grinberg "else " \ 160b09bf723SIgor Grinberg "if run loaduimage; then " \ 161b09bf723SIgor Grinberg "run mmcboot; " \ 162b09bf723SIgor Grinberg "else run nandboot; " \ 163b09bf723SIgor Grinberg "fi; " \ 164b09bf723SIgor Grinberg "fi; " \ 165b09bf723SIgor Grinberg "else run nandboot; fi" 166b09bf723SIgor Grinberg 167b09bf723SIgor Grinberg /* 168b09bf723SIgor Grinberg * Miscellaneous configurable options 169b09bf723SIgor Grinberg */ 170b09bf723SIgor Grinberg #define CONFIG_AUTO_COMPLETE 171b09bf723SIgor Grinberg #define CONFIG_CMDLINE_EDITING 172b09bf723SIgor Grinberg #define CONFIG_TIMESTAMP 173b09bf723SIgor Grinberg #define CONFIG_SYS_AUTOLOAD "no" 174b09bf723SIgor Grinberg #define CONFIG_SYS_LONGHELP /* undef to save memory */ 175b09bf723SIgor Grinberg #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 176b09bf723SIgor Grinberg #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ 177b09bf723SIgor Grinberg 178b09bf723SIgor Grinberg #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) 179b09bf723SIgor Grinberg 180b09bf723SIgor Grinberg /* 181b09bf723SIgor Grinberg * AM3517 has 12 GP timers, they can be driven by the system clock 182b09bf723SIgor Grinberg * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 183b09bf723SIgor Grinberg * This rate is divided by a local divisor. 184b09bf723SIgor Grinberg */ 185b09bf723SIgor Grinberg #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) 186b09bf723SIgor Grinberg #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 187b09bf723SIgor Grinberg #define CONFIG_SYS_HZ 1000 188b09bf723SIgor Grinberg 189b09bf723SIgor Grinberg /*----------------------------------------------------------------------- 190b09bf723SIgor Grinberg * Physical Memory Map 191b09bf723SIgor Grinberg */ 192b09bf723SIgor Grinberg #define CONFIG_NR_DRAM_BANKS 1 /* CM-T3517 DRAM is only on CS0 */ 193b09bf723SIgor Grinberg #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 194b09bf723SIgor Grinberg #define CONFIG_SYS_CS0_SIZE (256 << 20) 195b09bf723SIgor Grinberg 196b09bf723SIgor Grinberg /*----------------------------------------------------------------------- 197b09bf723SIgor Grinberg * FLASH and environment organization 198b09bf723SIgor Grinberg */ 199b09bf723SIgor Grinberg 200b09bf723SIgor Grinberg /* **** PISMO SUPPORT *** */ 201b09bf723SIgor Grinberg /* Monitor at start of flash */ 202b09bf723SIgor Grinberg #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 203b09bf723SIgor Grinberg #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 204b09bf723SIgor Grinberg 205b09bf723SIgor Grinberg #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 206b09bf723SIgor Grinberg #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 207b09bf723SIgor Grinberg #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 208b09bf723SIgor Grinberg 209a8a78c74SIgor Grinberg #if defined(CONFIG_CMD_NET) 210a8a78c74SIgor Grinberg #define CONFIG_DRIVER_TI_EMAC 211a8a78c74SIgor Grinberg #define CONFIG_DRIVER_TI_EMAC_USE_RMII 212a8a78c74SIgor Grinberg #define CONFIG_MII 213a8a78c74SIgor Grinberg #define CONFIG_SMC911X 214a8a78c74SIgor Grinberg #define CONFIG_SMC911X_32_BIT 215a8a78c74SIgor Grinberg #define CONFIG_SMC911X_BASE (0x2C000000 + (16 << 20)) 216e093d0b2SDmitry Lifshitz #define CONFIG_ARP_TIMEOUT 200UL 217e093d0b2SDmitry Lifshitz #define CONFIG_NET_RETRY_COUNT 5 218a8a78c74SIgor Grinberg #endif /* CONFIG_CMD_NET */ 219a8a78c74SIgor Grinberg 220b09bf723SIgor Grinberg /* additions for new relocation code, must be added to all boards */ 221b09bf723SIgor Grinberg #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 222b09bf723SIgor Grinberg #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 223b09bf723SIgor Grinberg #define CONFIG_SYS_INIT_RAM_SIZE 0x800 224b09bf723SIgor Grinberg #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 225b09bf723SIgor Grinberg CONFIG_SYS_INIT_RAM_SIZE - \ 226b09bf723SIgor Grinberg GENERATED_GBL_DATA_SIZE) 227b09bf723SIgor Grinberg 228b09bf723SIgor Grinberg /* Status LED */ 229b09bf723SIgor Grinberg #define GREEN_LED_GPIO 186 /* CM-T3517 Green LED is GPIO186 */ 230b09bf723SIgor Grinberg 23140bbd52aSIgor Grinberg /* Display Configuration */ 23240bbd52aSIgor Grinberg #define CONFIG_VIDEO_OMAP3 23340bbd52aSIgor Grinberg #define LCD_BPP LCD_COLOR16 23440bbd52aSIgor Grinberg 23540bbd52aSIgor Grinberg #define CONFIG_SPLASH_SCREEN 23640bbd52aSIgor Grinberg #define CONFIG_SPLASHIMAGE_GUARD 23740bbd52aSIgor Grinberg #define CONFIG_BMP_16BPP 23840bbd52aSIgor Grinberg #define CONFIG_SCF0403_LCD 23940bbd52aSIgor Grinberg 240*19a90ed6SNikita Kiryanov /* EEPROM */ 241*19a90ed6SNikita Kiryanov #define CONFIG_ENV_EEPROM_IS_ON_I2C 242*19a90ed6SNikita Kiryanov #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 243*19a90ed6SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 244*19a90ed6SNikita Kiryanov #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 245*19a90ed6SNikita Kiryanov #define CONFIG_SYS_EEPROM_SIZE 256 246*19a90ed6SNikita Kiryanov 247b09bf723SIgor Grinberg #endif /* __CONFIG_H */ 248