xref: /rk3399_rockchip-uboot/include/configs/chromebook_link.h (revision 8ef07571a0300e6ae84931c63d5eb3b2310c8aba)
1 /*
2  * Copyright (c) 2011 The Chromium OS Authors.
3  * (C) Copyright 2008
4  * Graeme Russ, graeme.russ@gmail.com.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 /*
10  * board/config.h - configuration options, board specific
11  */
12 
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15 
16 #include <configs/x86-common.h>
17 
18 #define CONFIG_SYS_CAR_ADDR			0xff7e0000
19 #define CONFIG_SYS_CAR_SIZE			(128 * 1024)
20 #define CONFIG_SYS_MONITOR_LEN			(1 << 20)
21 #define CONFIG_BOARD_EARLY_INIT_R
22 
23 #define CONFIG_NR_DRAM_BANKS			8
24 
25 #define CONFIG_COREBOOT_SERIAL
26 
27 #define CONFIG_SCSI_DEV_LIST		{PCI_VENDOR_ID_INTEL, \
28 			PCI_DEVICE_ID_INTEL_NM10_AHCI},	      \
29 	{PCI_VENDOR_ID_INTEL,		\
30 			PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
31 	{PCI_VENDOR_ID_INTEL, \
32 			PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
33 	{PCI_VENDOR_ID_INTEL,		\
34 			PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
35 
36 /*
37  * These common x86 features are not yet supported, but are added in
38  * follow-on patches in this series. Add undefs here to avoid every patch
39  * having to put things back into x86-common.h
40  */
41 #undef CONFIG_INTEL_ICH6_GPIO
42 #undef CONFIG_DM_GPIO
43 #undef CONFIG_CMD_GPIO
44 #undef CONFIG_VIDEO
45 #undef CONFIG_CFB_CONSOLE
46 #undef CONFIG_SYS_EARLY_PCI_INIT
47 #undef CONFIG_PCI
48 #undef CONFIG_ICH_SPI
49 #undef CONFIG_SPI
50 #undef CONFIG_CMD_SPI
51 #undef CONFIG_CMD_SF
52 #undef CONFIG_USB_EHCI
53 #undef CONFIG_CMD_USB
54 #undef CONFIG_CMD_SCSI
55 
56 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
57 					"stdout=vga,serial\0" \
58 					"stderr=vga,serial\0"
59 
60 #endif	/* __CONFIG_H */
61