xref: /rk3399_rockchip-uboot/include/configs/chromebook_link.h (revision 3ac839352db2fb464e1e6e6a4bc50f06fb29cdb0)
1 /*
2  * Copyright (c) 2011 The Chromium OS Authors.
3  * (C) Copyright 2008
4  * Graeme Russ, graeme.russ@gmail.com.
5  *
6  * SPDX-License-Identifier:	GPL-2.0+
7  */
8 
9 /*
10  * board/config.h - configuration options, board specific
11  */
12 
13 #ifndef __CONFIG_H
14 #define __CONFIG_H
15 
16 #include <configs/x86-common.h>
17 
18 #define CONFIG_SYS_CAR_ADDR			0xff7e0000
19 #define CONFIG_SYS_CAR_SIZE			(128 * 1024)
20 #define CONFIG_SYS_MONITOR_LEN			(1 << 20)
21 #define CONFIG_DCACHE_RAM_MRC_VAR_SIZE		0x4000
22 #define CONFIG_SYS_X86_START16			0xfffff800
23 #define CONFIG_BOARD_EARLY_INIT_F
24 #define CONFIG_DISPLAY_CPUINFO
25 
26 #define CONFIG_X86_RESET_VECTOR
27 #define CONFIG_NR_DRAM_BANKS			8
28 #define CONFIG_X86_MRC_START			0xfffa0000
29 #define CONFIG_CACHE_MRC_SIZE_KB		512
30 
31 #define CONFIG_COREBOOT_SERIAL
32 
33 #define CONFIG_SCSI_DEV_LIST		{PCI_VENDOR_ID_INTEL, \
34 			PCI_DEVICE_ID_INTEL_NM10_AHCI},	      \
35 	{PCI_VENDOR_ID_INTEL,		\
36 			PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \
37 	{PCI_VENDOR_ID_INTEL, \
38 			PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \
39 	{PCI_VENDOR_ID_INTEL,		\
40 			PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
41 
42 /*
43  * These common x86 features are not yet supported, but are added in
44  * follow-on patches in this series. Add undefs here to avoid every patch
45  * having to put things back into x86-common.h
46  */
47 #undef CONFIG_VIDEO
48 #undef CONFIG_CFB_CONSOLE
49 #undef CONFIG_ICH_SPI
50 #undef CONFIG_SPI
51 #undef CONFIG_CMD_SPI
52 #undef CONFIG_CMD_SF
53 #undef CONFIG_USB_EHCI
54 #undef CONFIG_CMD_USB
55 #undef CONFIG_CMD_SCSI
56 
57 #define CONFIG_PCI_MEM_BUS	0xe0000000
58 #define CONFIG_PCI_MEM_PHYS	CONFIG_PCI_MEM_BUS
59 #define CONFIG_PCI_MEM_SIZE	0x10000000
60 
61 #define CONFIG_PCI_PREF_BUS	0xd0000000
62 #define CONFIG_PCI_PREF_PHYS	CONFIG_PCI_PREF_BUS
63 #define CONFIG_PCI_PREF_SIZE	0x10000000
64 
65 #define CONFIG_PCI_IO_BUS	0x1000
66 #define CONFIG_PCI_IO_PHYS	CONFIG_PCI_IO_BUS
67 #define CONFIG_PCI_IO_SIZE	0xefff
68 
69 #define CONFIG_SYS_EARLY_PCI_INIT
70 #define CONFIG_PCI_PNP
71 
72 #define CONFIG_STD_DEVICES_SETTINGS     "stdin=usbkbd,vga,serial\0" \
73 					"stdout=vga,serial\0" \
74 					"stderr=vga,serial\0"
75 
76 #endif	/* __CONFIG_H */
77