xref: /rk3399_rockchip-uboot/include/configs/cgtqmx6eval.h (revision e404ade42d72513ea51d66b9474bcce194bab848)
1 /*
2  *
3  * Congatec Conga-QEVAl board configuration file.
4  *
5  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
6  * Based on Freescale i.MX6Q Sabre Lite board configuration file.
7  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
8  * Leo Sartre, <lsartre@adeneo-embedded.com>
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #ifndef __CONFIG_CGTQMX6EVAL_H
14 #define __CONFIG_CGTQMX6EVAL_H
15 
16 #include "mx6_common.h"
17 
18 #define CONFIG_MACH_TYPE	4122
19 
20 #ifdef CONFIG_SPL
21 #define CONFIG_SPL_SPI_SUPPORT
22 #define CONFIG_SYS_SPI_U_BOOT_OFFS	(64 * 1024)
23 #define CONFIG_SPL_SPI_LOAD
24 #include "imx6_spl.h"
25 #endif
26 
27 /* Size of malloc() pool */
28 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
29 
30 #define CONFIG_BOARD_EARLY_INIT_F
31 #define CONFIG_BOARD_LATE_INIT
32 #define CONFIG_MISC_INIT_R
33 
34 #define CONFIG_MXC_UART
35 #define CONFIG_MXC_UART_BASE	       UART2_BASE
36 
37 /* MMC Configs */
38 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
39 
40 /* SPI NOR */
41 #define CONFIG_SPI_FLASH
42 #define CONFIG_SPI_FLASH_STMICRO
43 #define CONFIG_SPI_FLASH_SST
44 #define CONFIG_MXC_SPI
45 #define CONFIG_SF_DEFAULT_BUS		0
46 #define CONFIG_SF_DEFAULT_SPEED		20000000
47 #define CONFIG_SF_DEFAULT_MODE		(SPI_MODE_0)
48 
49 /* Miscellaneous commands */
50 #define CONFIG_CMD_BMODE
51 
52 /* Thermal support */
53 #define CONFIG_IMX_THERMAL
54 
55 /* I2C Configs */
56 #define CONFIG_SYS_I2C
57 #define CONFIG_SYS_I2C_MXC
58 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
59 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
60 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
61 #define CONFIG_SYS_I2C_SPEED		  100000
62 
63 /* PMIC */
64 #define CONFIG_POWER
65 #define CONFIG_POWER_I2C
66 #define CONFIG_POWER_PFUZE100
67 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
68 
69 /* USB Configs */
70 #define CONFIG_USB_EHCI
71 #define CONFIG_USB_EHCI_MX6
72 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
73 #define CONFIG_USB_HOST_ETHER
74 #define CONFIG_USB_ETHER_ASIX
75 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
76 #define CONFIG_MXC_USB_FLAGS	0
77 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
78 #define CONFIG_USB_KEYBOARD
79 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
80 
81 #define CONFIG_USBD_HS
82 
83 #define CONFIG_USB_FUNCTION_MASS_STORAGE
84 
85 /* USB Device Firmware Update support */
86 #define CONFIG_USB_FUNCTION_DFU
87 #define CONFIG_DFU_MMC
88 #define CONFIG_DFU_SF
89 
90 #define CONFIG_USB_FUNCTION_FASTBOOT
91 #define CONFIG_CMD_FASTBOOT
92 #define CONFIG_ANDROID_BOOT_IMAGE
93 #define CONFIG_FASTBOOT_BUF_ADDR   CONFIG_SYS_LOAD_ADDR
94 #define CONFIG_FASTBOOT_BUF_SIZE   0x07000000
95 
96 /* Framebuffer */
97 #define CONFIG_VIDEO
98 #define CONFIG_VIDEO_IPUV3
99 #define CONFIG_CFB_CONSOLE
100 #define CONFIG_VGA_AS_SINGLE_DEVICE
101 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
102 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
103 #define CONFIG_VIDEO_BMP_RLE8
104 #define CONFIG_SPLASH_SCREEN
105 #define CONFIG_SPLASH_SCREEN_ALIGN
106 #define CONFIG_BMP_16BPP
107 #define CONFIG_VIDEO_LOGO
108 #define CONFIG_VIDEO_BMP_LOGO
109 #ifdef CONFIG_MX6DL
110 #define CONFIG_IPUV3_CLK 198000000
111 #else
112 #define CONFIG_IPUV3_CLK 264000000
113 #endif
114 #define CONFIG_IMX_HDMI
115 
116 /* SATA */
117 #define CONFIG_CMD_SATA
118 #define CONFIG_DWC_AHSATA
119 #define CONFIG_SYS_SATA_MAX_DEVICE	1
120 #define CONFIG_DWC_AHSATA_PORT_ID	0
121 #define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
122 #define CONFIG_LBA48
123 #define CONFIG_LIBATA
124 
125 /* Ethernet */
126 #define CONFIG_FEC_MXC
127 #define CONFIG_MII
128 #define IMX_FEC_BASE			ENET_BASE_ADDR
129 #define CONFIG_FEC_XCV_TYPE		RGMII
130 #define CONFIG_ETHPRIME			"FEC"
131 #define CONFIG_FEC_MXC_PHYADDR		6
132 #define CONFIG_PHYLIB
133 #define CONFIG_PHY_ATHEROS
134 
135 /* Command definition */
136 
137 #define CONFIG_MXC_UART_BASE	UART2_BASE
138 #define CONFIG_CONSOLE_DEV	"ttymxc1"
139 #define CONFIG_MMCROOT		"/dev/mmcblk0p2"
140 #define CONFIG_SYS_MMC_ENV_DEV		0
141 
142 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
143 #define CONFIG_EXTRA_ENV_SETTINGS \
144 	"script=boot.scr\0" \
145 	"image=zImage\0" \
146 	"fdtfile=undefined\0" \
147 	"fdt_addr_r=0x18000000\0" \
148 	"boot_fdt=try\0" \
149 	"ip_dyn=yes\0" \
150 	"console=" CONFIG_CONSOLE_DEV "\0" \
151 	"dfuspi=dfu 0 sf 0:0:10000000:0\0" \
152 	"dfu_alt_info_spl=spl raw 0x400\0" \
153 	"dfu_alt_info_img=u-boot raw 0x10000\0" \
154 	"dfu_alt_info=spl raw 0x400\0" \
155 	"bootm_size=0x10000000\0" \
156 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
157 	"mmcpart=1\0" \
158 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
159 	"update_sd_firmware=" \
160 		"if test ${ip_dyn} = yes; then " \
161 			"setenv get_cmd dhcp; " \
162 		"else " \
163 			"setenv get_cmd tftp; " \
164 		"fi; " \
165 		"if mmc dev ${mmcdev}; then "	\
166 			"if ${get_cmd} ${update_sd_firmware_filename}; then " \
167 				"setexpr fw_sz ${filesize} / 0x200; " \
168 				"setexpr fw_sz ${fw_sz} + 1; "	\
169 				"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
170 			"fi; "	\
171 		"fi\0" \
172 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
173 		"root=${mmcroot}\0" \
174 	"loadbootscript=" \
175 		"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
176 	"bootscript=echo Running bootscript from mmc ...; " \
177 		"source\0" \
178 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
179 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \
180 	"mmcboot=echo Booting from mmc ...; " \
181 		"run mmcargs; " \
182 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
183 			"if run loadfdt; then " \
184 				"bootz ${loadaddr} - ${fdt_addr_r}; " \
185 			"else " \
186 				"if test ${boot_fdt} = try; then " \
187 					"bootz; " \
188 				"else " \
189 					"echo WARN: Cannot load the DT; " \
190 				"fi; " \
191 			"fi; " \
192 		"else " \
193 			"bootz; " \
194 		"fi;\0" \
195 	"findfdt="\
196 		"if test $board_rev = MX6Q ; then " \
197 			"setenv fdtfile imx6q-qmx6.dtb; fi; " \
198 		"if test $board_rev = MX6DL ; then " \
199 			"setenv fdtfile imx6dl-qmx6.dtb; fi; " \
200 		"if test $fdtfile = undefined; then " \
201 			"echo WARNING: Could not determine dtb to use; fi; \0" \
202 	"netargs=setenv bootargs console=${console},${baudrate} " \
203 		"root=/dev/nfs " \
204 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
205 	"netboot=echo Booting from net ...; " \
206 		"run netargs; " \
207 		"if test ${ip_dyn} = yes; then " \
208 			"setenv get_cmd dhcp; " \
209 		"else " \
210 			"setenv get_cmd tftp; " \
211 		"fi; " \
212 		"${get_cmd} ${image}; " \
213 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
214 			"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
215 				"bootz ${loadaddr} - ${fdt_addr_r}; " \
216 			"else " \
217 				"if test ${boot_fdt} = try; then " \
218 					"bootz; " \
219 				"else " \
220 					"echo WARN: Cannot load the DT; " \
221 				"fi; " \
222 			"fi; " \
223 		"else " \
224 			"bootz; " \
225 		"fi;\0" \
226 	"spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\
227 
228 #define CONFIG_BOOTCOMMAND \
229 	"run spilock;"	    \
230 	"run findfdt; "	\
231 	"mmc dev ${mmcdev};" \
232 	"if mmc rescan; then " \
233 		"if run loadbootscript; then " \
234 		"run bootscript; " \
235 		"else " \
236 			"if run loadimage; then " \
237 				"run mmcboot; " \
238 			"else run netboot; " \
239 			"fi; " \
240 		"fi; " \
241 	"else run netboot; fi"
242 
243 #define CONFIG_SYS_MEMTEST_START       0x10000000
244 #define CONFIG_SYS_MEMTEST_END	       0x10010000
245 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
246 
247 /* Physical Memory Map */
248 #define CONFIG_NR_DRAM_BANKS	       1
249 #define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
250 
251 #define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
252 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
253 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
254 
255 #define CONFIG_SYS_INIT_SP_OFFSET \
256 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
257 #define CONFIG_SYS_INIT_SP_ADDR \
258 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
259 
260 /* Environment organization */
261 #if defined (CONFIG_ENV_IS_IN_MMC)
262 #define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
263 #define CONFIG_SYS_MMC_ENV_DEV		0
264 #endif
265 
266 #define CONFIG_ENV_SIZE			(8 * 1024)
267 
268 #define CONFIG_ENV_IS_IN_SPI_FLASH
269 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH)
270 #define CONFIG_ENV_OFFSET		(768 * 1024)
271 #define CONFIG_ENV_SECT_SIZE		(64 * 1024)
272 #define CONFIG_ENV_SPI_BUS		CONFIG_SF_DEFAULT_BUS
273 #define CONFIG_ENV_SPI_CS		CONFIG_SF_DEFAULT_CS
274 #define CONFIG_ENV_SPI_MODE		CONFIG_SF_DEFAULT_MODE
275 #define CONFIG_ENV_SPI_MAX_HZ		CONFIG_SF_DEFAULT_SPEED
276 #endif
277 
278 #endif			       /* __CONFIG_CGTQMX6EVAL_H */
279