xref: /rk3399_rockchip-uboot/include/configs/cgtqmx6eval.h (revision 95246ac7094cd511f02f98d403c965625ea81db4)
1 /*
2  *
3  * Congatec Conga-QEVAl board configuration file.
4  *
5  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
6  * Based on Freescale i.MX6Q Sabre Lite board configuration file.
7  * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
8  * Leo Sartre, <lsartre@adeneo-embedded.com>
9  *
10  * SPDX-License-Identifier:	GPL-2.0+
11  */
12 
13 #ifndef __CONFIG_CGTQMX6EVAL_H
14 #define __CONFIG_CGTQMX6EVAL_H
15 
16 #include "mx6_common.h"
17 
18 #define CONFIG_MACH_TYPE	4122
19 
20 /* Size of malloc() pool */
21 #define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)
22 
23 #define CONFIG_BOARD_EARLY_INIT_F
24 #define CONFIG_MISC_INIT_R
25 
26 #define CONFIG_MXC_UART
27 #define CONFIG_MXC_UART_BASE	       UART2_BASE
28 
29 /* MMC Configs */
30 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
31 
32 /* Miscellaneous commands */
33 #define CONFIG_CMD_BMODE
34 
35 /* Thermal support */
36 #define CONFIG_IMX6_THERMAL
37 
38 #define CONFIG_CMD_FUSE
39 #if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
40 #define CONFIG_MXC_OCOTP
41 #endif
42 
43 /* I2C Configs */
44 #define CONFIG_CMD_I2C
45 #define CONFIG_SYS_I2C
46 #define CONFIG_SYS_I2C_MXC
47 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
48 #define CONFIG_SYS_I2C_SPEED		  100000
49 
50 /* PMIC */
51 #define CONFIG_POWER
52 #define CONFIG_POWER_I2C
53 #define CONFIG_POWER_PFUZE100
54 #define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
55 
56 /* USB Configs */
57 #define CONFIG_CMD_USB
58 #define CONFIG_CMD_FAT
59 #define CONFIG_USB_EHCI
60 #define CONFIG_USB_EHCI_MX6
61 #define CONFIG_USB_STORAGE
62 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
63 #define CONFIG_USB_HOST_ETHER
64 #define CONFIG_USB_ETHER_ASIX
65 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
66 #define CONFIG_MXC_USB_FLAGS	0
67 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */
68 #define CONFIG_USB_KEYBOARD
69 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
70 
71 #define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
72 
73 #define CONFIG_EXTRA_ENV_SETTINGS \
74 	"script=boot.scr\0" \
75 	"image=zImage\0" \
76 	"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
77 	"boot_dir=/boot\0" \
78 	"console=ttymxc1\0" \
79 	"fdt_high=0xffffffff\0" \
80 	"initrd_high=0xffffffff\0" \
81 	"fdt_addr=0x18000000\0" \
82 	"boot_fdt=try\0" \
83 	"mmcdev=1\0" \
84 	"mmcpart=1\0" \
85 	"mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
86 	"mmcargs=setenv bootargs console=${console},${baudrate} " \
87 		"root=${mmcroot}\0" \
88 	"loadbootscript=" \
89 		"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
90 	"bootscript=echo Running bootscript from mmc ...; " \
91 		"source\0" \
92 	"loadimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
93 		"${boot_dir}/${image}\0" \
94 	"loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
95 		"${boot_dir}/${fdt_file}\0" \
96 	"mmcboot=echo Booting from mmc ...; " \
97 		"run mmcargs; " \
98 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
99 			"if run loadfdt; then " \
100 				"bootz ${loadaddr} - ${fdt_addr}; " \
101 			"else " \
102 				"if test ${boot_fdt} = try; then " \
103 					"bootz; " \
104 				"else " \
105 					"echo WARN: Cannot load the DT; " \
106 				"fi; " \
107 			"fi; " \
108 		"else " \
109 			"bootz; " \
110 		"fi;\0"
111 
112 #define CONFIG_BOOTCOMMAND \
113 	   "mmc dev ${mmcdev};" \
114 	   "mmc dev ${mmcdev}; if mmc rescan; then " \
115 		   "if run loadbootscript; then " \
116 			   "run bootscript; " \
117 		   "else " \
118 			   "if run loadimage; then " \
119 				   "run mmcboot; " \
120 			   "else "\
121 				   "echo ERR: Fail to boot from mmc; " \
122 			   "fi; " \
123 		   "fi; " \
124 	   "else echo ERR: Fail to boot from mmc; fi"
125 
126 #define CONFIG_SYS_MEMTEST_START       0x10000000
127 #define CONFIG_SYS_MEMTEST_END	       0x10010000
128 #define CONFIG_SYS_MEMTEST_SCRATCH     0x10800000
129 
130 /* Physical Memory Map */
131 #define CONFIG_NR_DRAM_BANKS	       1
132 #define PHYS_SDRAM		       MMDC0_ARB_BASE_ADDR
133 #define PHYS_SDRAM_SIZE			       (1u * 1024 * 1024 * 1024)
134 
135 #define CONFIG_SYS_SDRAM_BASE	       PHYS_SDRAM
136 #define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
137 #define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
138 
139 #define CONFIG_SYS_INIT_SP_OFFSET \
140 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
141 #define CONFIG_SYS_INIT_SP_ADDR \
142 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
143 
144 /* Environment organization */
145 #define CONFIG_ENV_SIZE			(8 * 1024)
146 
147 #define CONFIG_ENV_IS_IN_MMC
148 
149 #define CONFIG_ENV_OFFSET		(6 * 64 * 1024)
150 #define CONFIG_SYS_MMC_ENV_DEV		0
151 
152 #endif			       /* __CONFIG_CGTQMX6EVAL_H */
153