1 /* 2 * 3 * Congatec Conga-QEVAl board configuration file. 4 * 5 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. 6 * Based on Freescale i.MX6Q Sabre Lite board configuration file. 7 * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> 8 * Leo Sartre, <lsartre@adeneo-embedded.com> 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_CGTQMX6EVAL_H 14 #define __CONFIG_CGTQMX6EVAL_H 15 16 #include "mx6_common.h" 17 18 #define CONFIG_MACH_TYPE 4122 19 20 #ifdef CONFIG_SPL 21 #define CONFIG_SPL_LIBCOMMON_SUPPORT 22 #define CONFIG_SPL_MMC_SUPPORT 23 #define CONFIG_SPL_SPI_SUPPORT 24 #define CONFIG_SPL_SPI_FLASH_SUPPORT 25 #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) 26 #define CONFIG_SPL_SPI_LOAD 27 #include "imx6_spl.h" 28 #endif 29 30 /* Size of malloc() pool */ 31 #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) 32 33 #define CONFIG_BOARD_EARLY_INIT_F 34 #define CONFIG_BOARD_LATE_INIT 35 #define CONFIG_MISC_INIT_R 36 37 #define CONFIG_MXC_UART 38 #define CONFIG_MXC_UART_BASE UART2_BASE 39 40 /* MMC Configs */ 41 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 42 43 /* SPI NOR */ 44 #define CONFIG_SPI_FLASH 45 #define CONFIG_SPI_FLASH_STMICRO 46 #define CONFIG_SPI_FLASH_SST 47 #define CONFIG_MXC_SPI 48 #define CONFIG_SF_DEFAULT_BUS 0 49 #define CONFIG_SF_DEFAULT_SPEED 20000000 50 #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) 51 52 /* Miscellaneous commands */ 53 #define CONFIG_CMD_BMODE 54 55 /* Thermal support */ 56 #define CONFIG_IMX_THERMAL 57 58 /* I2C Configs */ 59 #define CONFIG_SYS_I2C 60 #define CONFIG_SYS_I2C_MXC 61 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 62 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 63 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 64 #define CONFIG_SYS_I2C_SPEED 100000 65 66 /* PMIC */ 67 #define CONFIG_POWER 68 #define CONFIG_POWER_I2C 69 #define CONFIG_POWER_PFUZE100 70 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 71 72 /* USB Configs */ 73 #define CONFIG_CMD_FAT 74 #define CONFIG_USB_EHCI 75 #define CONFIG_USB_EHCI_MX6 76 #define CONFIG_USB_STORAGE 77 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET 78 #define CONFIG_USB_HOST_ETHER 79 #define CONFIG_USB_ETHER_ASIX 80 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 81 #define CONFIG_MXC_USB_FLAGS 0 82 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ 83 #define CONFIG_USB_KEYBOARD 84 #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP 85 86 #define CONFIG_USBD_HS 87 88 #define CONFIG_CMD_USB_MASS_STORAGE 89 #define CONFIG_USB_FUNCTION_MASS_STORAGE 90 91 /* USB Device Firmware Update support */ 92 #define CONFIG_CMD_DFU 93 #define CONFIG_USB_FUNCTION_DFU 94 #define CONFIG_DFU_MMC 95 #define CONFIG_DFU_SF 96 97 #define CONFIG_USB_FUNCTION_FASTBOOT 98 #define CONFIG_CMD_FASTBOOT 99 #define CONFIG_ANDROID_BOOT_IMAGE 100 #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR 101 #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 102 103 /* Framebuffer */ 104 #define CONFIG_VIDEO 105 #define CONFIG_VIDEO_IPUV3 106 #define CONFIG_CFB_CONSOLE 107 #define CONFIG_VGA_AS_SINGLE_DEVICE 108 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 109 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 110 #define CONFIG_VIDEO_BMP_RLE8 111 #define CONFIG_SPLASH_SCREEN 112 #define CONFIG_SPLASH_SCREEN_ALIGN 113 #define CONFIG_BMP_16BPP 114 #define CONFIG_VIDEO_LOGO 115 #define CONFIG_VIDEO_BMP_LOGO 116 #ifdef CONFIG_MX6DL 117 #define CONFIG_IPUV3_CLK 198000000 118 #else 119 #define CONFIG_IPUV3_CLK 264000000 120 #endif 121 #define CONFIG_IMX_HDMI 122 123 /* SATA */ 124 #define CONFIG_CMD_SATA 125 #define CONFIG_DWC_AHSATA 126 #define CONFIG_SYS_SATA_MAX_DEVICE 1 127 #define CONFIG_DWC_AHSATA_PORT_ID 0 128 #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR 129 #define CONFIG_LBA48 130 #define CONFIG_LIBATA 131 132 /* Ethernet */ 133 #define CONFIG_CMD_MII 134 #define CONFIG_FEC_MXC 135 #define CONFIG_MII 136 #define IMX_FEC_BASE ENET_BASE_ADDR 137 #define CONFIG_FEC_XCV_TYPE RGMII 138 #define CONFIG_ETHPRIME "FEC" 139 #define CONFIG_FEC_MXC_PHYADDR 6 140 #define CONFIG_PHYLIB 141 #define CONFIG_PHY_ATHEROS 142 143 /* Command definition */ 144 145 #define CONFIG_MXC_UART_BASE UART2_BASE 146 #define CONFIG_CONSOLE_DEV "ttymxc1" 147 #define CONFIG_MMCROOT "/dev/mmcblk0p2" 148 #define CONFIG_SYS_MMC_ENV_DEV 0 149 150 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 151 #define CONFIG_EXTRA_ENV_SETTINGS \ 152 "script=boot.scr\0" \ 153 "image=zImage\0" \ 154 "fdtfile=undefined\0" \ 155 "fdt_addr_r=0x18000000\0" \ 156 "boot_fdt=try\0" \ 157 "ip_dyn=yes\0" \ 158 "console=" CONFIG_CONSOLE_DEV "\0" \ 159 "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ 160 "dfu_alt_info_spl=spl raw 0x400\0" \ 161 "dfu_alt_info_img=u-boot raw 0x10000\0" \ 162 "dfu_alt_info=spl raw 0x400\0" \ 163 "bootm_size=0x10000000\0" \ 164 "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ 165 "mmcpart=1\0" \ 166 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 167 "update_sd_firmware=" \ 168 "if test ${ip_dyn} = yes; then " \ 169 "setenv get_cmd dhcp; " \ 170 "else " \ 171 "setenv get_cmd tftp; " \ 172 "fi; " \ 173 "if mmc dev ${mmcdev}; then " \ 174 "if ${get_cmd} ${update_sd_firmware_filename}; then " \ 175 "setexpr fw_sz ${filesize} / 0x200; " \ 176 "setexpr fw_sz ${fw_sz} + 1; " \ 177 "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ 178 "fi; " \ 179 "fi\0" \ 180 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 181 "root=${mmcroot}\0" \ 182 "loadbootscript=" \ 183 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 184 "bootscript=echo Running bootscript from mmc ...; " \ 185 "source\0" \ 186 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ 187 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ 188 "mmcboot=echo Booting from mmc ...; " \ 189 "run mmcargs; " \ 190 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 191 "if run loadfdt; then " \ 192 "bootz ${loadaddr} - ${fdt_addr_r}; " \ 193 "else " \ 194 "if test ${boot_fdt} = try; then " \ 195 "bootz; " \ 196 "else " \ 197 "echo WARN: Cannot load the DT; " \ 198 "fi; " \ 199 "fi; " \ 200 "else " \ 201 "bootz; " \ 202 "fi;\0" \ 203 "findfdt="\ 204 "if test $board_rev = MX6Q ; then " \ 205 "setenv fdtfile imx6q-qmx6.dtb; fi; " \ 206 "if test $board_rev = MX6DL ; then " \ 207 "setenv fdtfile imx6dl-qmx6.dtb; fi; " \ 208 "if test $fdtfile = undefined; then " \ 209 "echo WARNING: Could not determine dtb to use; fi; \0" \ 210 "netargs=setenv bootargs console=${console},${baudrate} " \ 211 "root=/dev/nfs " \ 212 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ 213 "netboot=echo Booting from net ...; " \ 214 "run netargs; " \ 215 "if test ${ip_dyn} = yes; then " \ 216 "setenv get_cmd dhcp; " \ 217 "else " \ 218 "setenv get_cmd tftp; " \ 219 "fi; " \ 220 "${get_cmd} ${image}; " \ 221 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 222 "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ 223 "bootz ${loadaddr} - ${fdt_addr_r}; " \ 224 "else " \ 225 "if test ${boot_fdt} = try; then " \ 226 "bootz; " \ 227 "else " \ 228 "echo WARN: Cannot load the DT; " \ 229 "fi; " \ 230 "fi; " \ 231 "else " \ 232 "bootz; " \ 233 "fi;\0" \ 234 "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\ 235 236 #define CONFIG_BOOTCOMMAND \ 237 "run spilock;" \ 238 "run findfdt; " \ 239 "mmc dev ${mmcdev};" \ 240 "if mmc rescan; then " \ 241 "if run loadbootscript; then " \ 242 "run bootscript; " \ 243 "else " \ 244 "if run loadimage; then " \ 245 "run mmcboot; " \ 246 "else run netboot; " \ 247 "fi; " \ 248 "fi; " \ 249 "else run netboot; fi" 250 251 #define CONFIG_SYS_MEMTEST_START 0x10000000 252 #define CONFIG_SYS_MEMTEST_END 0x10010000 253 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 254 255 /* Physical Memory Map */ 256 #define CONFIG_NR_DRAM_BANKS 1 257 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 258 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 259 260 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 261 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 262 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 263 264 #define CONFIG_SYS_INIT_SP_OFFSET \ 265 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 266 #define CONFIG_SYS_INIT_SP_ADDR \ 267 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 268 269 /* Environment organization */ 270 #if defined (CONFIG_ENV_IS_IN_MMC) 271 #define CONFIG_ENV_OFFSET (6 * 64 * 1024) 272 #define CONFIG_SYS_MMC_ENV_DEV 0 273 #endif 274 275 #define CONFIG_ENV_SIZE (8 * 1024) 276 277 #define CONFIG_ENV_IS_IN_SPI_FLASH 278 #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) 279 #define CONFIG_ENV_OFFSET (768 * 1024) 280 #define CONFIG_ENV_SECT_SIZE (64 * 1024) 281 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 282 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 283 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 284 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 285 #endif 286 287 #endif /* __CONFIG_CGTQMX6EVAL_H */ 288