1 /* 2 * bur_am335x_common.h 3 * 4 * common parts used by B&R AM335x based boards 5 * 6 * Copyright (C) 2013 Hannes Schmelzer <oe5hpm@oevsv.at> - 7 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #ifndef __BUR_AM335X_COMMON_H__ 13 #define __BUR_AM335X_COMMON_H__ 14 /* ------------------------------------------------------------------------- */ 15 #define BUR_COMMON_ENV \ 16 "usbscript=usb start && fatload usb 0 0x80000000 usbscript.img && source\0" \ 17 "brdefaultip=if test -r ${ipaddr}; then; else" \ 18 " setenv ipaddr 192.168.60.1; setenv serverip 192.168.60.254;" \ 19 " setenv gatewayip 192.168.60.254; setenv netmask 255.255.255.0; fi;\0" \ 20 "netconsole=echo switching to network console ...; " \ 21 "if dhcp; then; else run brdefaultip; fi; setenv ncip ${serverip}; " \ 22 "setcurs 1 9; lcdputs myip; setcurs 10 9; lcdputs ${ipaddr};" \ 23 "setcurs 1 10;lcdputs serverip; setcurs 10 10; lcdputs ${serverip};" \ 24 "setenv stdout nc;setenv stdin nc;setenv stderr nc\0" 25 26 #define CONFIG_PREBOOT "run brdefaultip" 27 28 29 #define CONFIG_AM33XX 30 #define CONFIG_OMAP 31 #define CONFIG_OMAP_COMMON 32 #define CONFIG_BOARD_LATE_INIT 33 #define CONFIG_SYS_CACHELINE_SIZE 64 34 #define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */ 35 36 /* Timer information */ 37 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 38 #define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */ 39 #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC /* enable 32kHz OSC at bootime */ 40 #define CONFIG_SPL_POWER_SUPPORT 41 #define CONFIG_POWER_TPS65217 42 43 #define CONFIG_SYS_NO_FLASH /* have no NOR-flash */ 44 45 #include <asm/arch/omap.h> 46 47 /* NS16550 Configuration */ 48 #define CONFIG_SYS_NS16550_SERIAL 49 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 50 #define CONFIG_SYS_NS16550_CLK 48000000 51 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ 52 #define CONFIG_BAUDRATE 115200 53 54 /* Network defines */ 55 #define CONFIG_BOOTP_DNS /* Configurable parts of CMD_DHCP */ 56 #define CONFIG_BOOTP_SEND_HOSTNAME 57 #define CONFIG_BOOTP_GATEWAY 58 #define CONFIG_BOOTP_SUBNETMASK 59 #define CONFIG_NET_RETRY_COUNT 2 60 #define CONFIG_DRIVER_TI_CPSW /* Driver for IP block */ 61 #define CONFIG_MII /* Required in net/eth.c */ 62 #define CONFIG_PHYLIB 63 #define CONFIG_PHY_NATSEMI 64 /* Network console */ 65 #define CONFIG_BOOTP_MAY_FAIL /* if we don't have DHCP environment */ 66 /* 67 * SPL related defines. The Public RAM memory map the ROM defines the 68 * area between 0x402F0400 and 0x4030B800 as a download area and 69 * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also 70 * supports X-MODEM loading via UART, and we leverage this and then use 71 * Y-MODEM to load u-boot.img, when booted over UART. 72 */ 73 #define CONFIG_SPL_TEXT_BASE 0x402F0400 74 #define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) 75 76 /* 77 * Since SPL did pll and ddr initialization for us, 78 * we don't need to do it twice. 79 */ 80 #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT) 81 #define CONFIG_SKIP_LOWLEVEL_INIT 82 #endif /* !CONFIG_SPL_BUILD, ... */ 83 /* 84 * Our DDR memory always starts at 0x80000000 and U-Boot shall have 85 * relocated itself to higher in memory by the time this value is used. 86 */ 87 #define CONFIG_SYS_LOAD_ADDR 0x80000000 88 /* 89 * ---------------------------------------------------------------------------- 90 * DDR information. We say (for simplicity) that we have 1 bank, 91 * always, even when we have more. We always start at 0x80000000, 92 * and we place the initial stack pointer in our SRAM. 93 */ 94 #define CONFIG_NR_DRAM_BANKS 1 95 #define CONFIG_SYS_SDRAM_BASE 0x80000000 96 #define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ 97 GENERATED_GBL_DATA_SIZE) 98 99 /* I2C */ 100 #define CONFIG_SYS_I2C 101 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 102 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 103 #define CONFIG_SYS_I2C_OMAP24XX 104 /* GPIO */ 105 #define CONFIG_OMAP_GPIO 106 /* 107 * ---------------------------------------------------------------------------- 108 * The following are general good-enough settings for U-Boot. We set a 109 * large malloc pool as we generally have a lot of DDR, and we opt for 110 * function over binary size in the main portion of U-Boot as this is 111 * generally easily constrained later if needed. We enable the config 112 * options that give us information in the environment about what board 113 * we are on so we do not need to rely on the command prompt. We set a 114 * console baudrate of 115200 and use the default baud rate table. 115 */ 116 #define CONFIG_SYS_MALLOC_LEN (5120 << 10) 117 #define CONFIG_SYS_CONSOLE_INFO_QUIET 118 #define CONFIG_ENV_OVERWRITE /* Overwrite ethaddr / serial# */ 119 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 120 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 121 122 /* As stated above, the following choices are optional. */ 123 #define CONFIG_SYS_LONGHELP 124 #define CONFIG_AUTO_COMPLETE 125 #define CONFIG_CMDLINE_EDITING 126 #define CONFIG_VERSION_VARIABLE 127 128 /* We set the max number of command args high to avoid HUSH bugs. */ 129 #define CONFIG_SYS_MAXARGS 64 130 131 /* Console I/O Buffer Size */ 132 #define CONFIG_SYS_CBSIZE 512 133 /* Print Buffer Size */ 134 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE +\ 135 sizeof(CONFIG_SYS_PROMPT) + 16) 136 /* Boot Argument Buffer Size */ 137 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 138 139 /* 140 * Our platforms make use of SPL to initalize the hardware (primarily 141 * memory) enough for full U-Boot to be loaded. We also support Falcon 142 * Mode so that the Linux kernel can be booted directly from SPL 143 * instead, if desired. We make use of the general SPL framework found 144 * under common/spl/. Given our generally common memory map, we set a 145 * number of related defaults and sizes here. 146 */ 147 #define CONFIG_SPL_FRAMEWORK 148 /* 149 * Place the image at the start of the ROM defined image space. 150 * We limit our size to the ROM-defined downloaded image area, and use the 151 * rest of the space for stack. We load U-Boot itself into memory at 152 * 0x80800000 for legacy reasons (to not conflict with older SPLs). We 153 * have our BSS be placed 1MiB after this, to allow for the default 154 * Linux kernel address of 0x80008000 to work, in the Falcon Mode case. 155 * We have the SPL malloc pool at the end of the BSS area. 156 * 157 * ---------------------------------------------------------------------------- 158 */ 159 #undef CONFIG_SYS_TEXT_BASE 160 #define CONFIG_SYS_TEXT_BASE 0x80800000 161 #define CONFIG_SPL_BSS_START_ADDR 0x80A00000 162 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 163 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ 164 CONFIG_SPL_BSS_MAX_SIZE) 165 #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN 166 167 /* General parts of the framework, required. */ 168 #define CONFIG_SPL_I2C_SUPPORT 169 #define CONFIG_SPL_LIBCOMMON_SUPPORT 170 #define CONFIG_SPL_LIBGENERIC_SUPPORT 171 #define CONFIG_SPL_SERIAL_SUPPORT 172 #define CONFIG_SPL_BOARD_INIT 173 #define CONFIG_SPL_YMODEM_SUPPORT 174 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" 175 176 #endif /* ! __BUR_AM335X_COMMON_H__ */ 177