xref: /rk3399_rockchip-uboot/include/configs/bur_am335x_common.h (revision c1b62ba9ca0e41fdd548cb3bb9af3b3f90d4a393)
1893c04e1SHannes Petermaier /*
2893c04e1SHannes Petermaier  * bur_am335x_common.h
3893c04e1SHannes Petermaier  *
4893c04e1SHannes Petermaier  * common parts used by B&R AM335x based boards
5893c04e1SHannes Petermaier  *
63b804d94SHannes Schmelzer  * Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
7893c04e1SHannes Petermaier  * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
8893c04e1SHannes Petermaier  *
9893c04e1SHannes Petermaier  * SPDX-License-Identifier:        GPL-2.0+
10893c04e1SHannes Petermaier  */
11893c04e1SHannes Petermaier 
12893c04e1SHannes Petermaier #ifndef __BUR_AM335X_COMMON_H__
13893c04e1SHannes Petermaier #define __BUR_AM335X_COMMON_H__
14893c04e1SHannes Petermaier /* ------------------------------------------------------------------------- */
15893c04e1SHannes Petermaier #define CONFIG_MAX_RAM_BANK_SIZE	(1024 << 20)	/* 1GB */
16893c04e1SHannes Petermaier 
17893c04e1SHannes Petermaier /* Timer information */
18893c04e1SHannes Petermaier #define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
19893c04e1SHannes Petermaier #define CONFIG_SYS_TIMERBASE		0x48040000	/* Use Timer2 */
2096de041eSHannes Petermaier #define CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC	/* enable 32kHz OSC at bootime */
21893c04e1SHannes Petermaier #define CONFIG_POWER_TPS65217
22893c04e1SHannes Petermaier 
23893c04e1SHannes Petermaier #include <asm/arch/omap.h>
24893c04e1SHannes Petermaier 
25893c04e1SHannes Petermaier /* NS16550 Configuration */
26893c04e1SHannes Petermaier #define CONFIG_SYS_NS16550_SERIAL
27893c04e1SHannes Petermaier #define CONFIG_SYS_NS16550_REG_SIZE	(-4)
28893c04e1SHannes Petermaier #define CONFIG_SYS_NS16550_CLK		48000000
29893c04e1SHannes Petermaier #define CONFIG_SYS_NS16550_COM1		0x44e09000	/* UART0 */
30893c04e1SHannes Petermaier 
31893c04e1SHannes Petermaier /* Network defines */
32893c04e1SHannes Petermaier #define CONFIG_DRIVER_TI_CPSW		/* Driver for IP block */
33893c04e1SHannes Petermaier #define CONFIG_MII			/* Required in net/eth.c */
34893c04e1SHannes Petermaier #define CONFIG_PHY_NATSEMI
353b804d94SHannes Schmelzer 
36893c04e1SHannes Petermaier /*
37893c04e1SHannes Petermaier  * SPL related defines.  The Public RAM memory map the ROM defines the
38893c04e1SHannes Petermaier  * area between 0x402F0400 and 0x4030B800 as a download area and
39893c04e1SHannes Petermaier  * 0x4030B800 to 0x4030CE00 as a public stack area.  The ROM also
40893c04e1SHannes Petermaier  * supports X-MODEM loading via UART, and we leverage this and then use
41*fa2f81b0STom Rini  * Y-MODEM to load u-boot.img, when booted over UART.  We must also include
42*fa2f81b0STom Rini  * the scratch space that U-Boot uses in SRAM.
43893c04e1SHannes Petermaier  */
44893c04e1SHannes Petermaier #define CONFIG_SPL_TEXT_BASE		0x402F0400
45*fa2f81b0STom Rini #define CONFIG_SPL_MAX_SIZE		(SRAM_SCRATCH_SPACE_ADDR - \
46*fa2f81b0STom Rini 					 CONFIG_SPL_TEXT_BASE)
47893c04e1SHannes Petermaier 
48893c04e1SHannes Petermaier /*
49893c04e1SHannes Petermaier  * Since SPL did pll and ddr initialization for us,
50893c04e1SHannes Petermaier  * we don't need to do it twice.
51893c04e1SHannes Petermaier  */
52893c04e1SHannes Petermaier #if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
53893c04e1SHannes Petermaier #define CONFIG_SKIP_LOWLEVEL_INIT
54893c04e1SHannes Petermaier #endif /* !CONFIG_SPL_BUILD, ... */
55893c04e1SHannes Petermaier /*
56893c04e1SHannes Petermaier  * Our DDR memory always starts at 0x80000000 and U-Boot shall have
57893c04e1SHannes Petermaier  * relocated itself to higher in memory by the time this value is used.
58893c04e1SHannes Petermaier  */
59893c04e1SHannes Petermaier #define CONFIG_SYS_LOAD_ADDR		0x80000000
60893c04e1SHannes Petermaier /*
61893c04e1SHannes Petermaier  * ----------------------------------------------------------------------------
62893c04e1SHannes Petermaier  * DDR information.  We say (for simplicity) that we have 1 bank,
63893c04e1SHannes Petermaier  * always, even when we have more.  We always start at 0x80000000,
64893c04e1SHannes Petermaier  * and we place the initial stack pointer in our SRAM.
65893c04e1SHannes Petermaier  */
66893c04e1SHannes Petermaier #define CONFIG_NR_DRAM_BANKS		1
67893c04e1SHannes Petermaier #define CONFIG_SYS_SDRAM_BASE		0x80000000
68893c04e1SHannes Petermaier #define CONFIG_SYS_INIT_SP_ADDR		(NON_SECURE_SRAM_END - \
69893c04e1SHannes Petermaier 					GENERATED_GBL_DATA_SIZE)
70893c04e1SHannes Petermaier 
71893c04e1SHannes Petermaier /* I2C */
72893c04e1SHannes Petermaier #define CONFIG_SYS_I2C
73893c04e1SHannes Petermaier #define CONFIG_SYS_OMAP24_I2C_SPEED	100000
74893c04e1SHannes Petermaier #define CONFIG_SYS_OMAP24_I2C_SLAVE	1
75893c04e1SHannes Petermaier 
76893c04e1SHannes Petermaier /*
77893c04e1SHannes Petermaier  * Our platforms make use of SPL to initalize the hardware (primarily
78893c04e1SHannes Petermaier  * memory) enough for full U-Boot to be loaded.  We also support Falcon
79893c04e1SHannes Petermaier  * Mode so that the Linux kernel can be booted directly from SPL
80893c04e1SHannes Petermaier  * instead, if desired.  We make use of the general SPL framework found
81893c04e1SHannes Petermaier  * under common/spl/.  Given our generally common memory map, we set a
82893c04e1SHannes Petermaier  * number of related defaults and sizes here.
83893c04e1SHannes Petermaier  */
84893c04e1SHannes Petermaier #define CONFIG_SPL_FRAMEWORK
85893c04e1SHannes Petermaier /*
86893c04e1SHannes Petermaier  * Place the image at the start of the ROM defined image space.
87893c04e1SHannes Petermaier  * We limit our size to the ROM-defined downloaded image area, and use the
88893c04e1SHannes Petermaier  * rest of the space for stack.  We load U-Boot itself into memory at
89893c04e1SHannes Petermaier  * 0x80800000 for legacy reasons (to not conflict with older SPLs).  We
90893c04e1SHannes Petermaier  * have our BSS be placed 1MiB after this, to allow for the default
91893c04e1SHannes Petermaier  * Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
92893c04e1SHannes Petermaier  * We have the SPL malloc pool at the end of the BSS area.
93893c04e1SHannes Petermaier  *
94893c04e1SHannes Petermaier  * ----------------------------------------------------------------------------
95893c04e1SHannes Petermaier  */
96893c04e1SHannes Petermaier #undef  CONFIG_SYS_TEXT_BASE
97893c04e1SHannes Petermaier #define CONFIG_SYS_TEXT_BASE		0x80800000
98893c04e1SHannes Petermaier #define CONFIG_SPL_BSS_START_ADDR	0x80A00000
99893c04e1SHannes Petermaier #define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
100893c04e1SHannes Petermaier #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
101893c04e1SHannes Petermaier 					CONFIG_SPL_BSS_MAX_SIZE)
102893c04e1SHannes Petermaier #define CONFIG_SYS_SPL_MALLOC_SIZE	CONFIG_SYS_MALLOC_LEN
103893c04e1SHannes Petermaier 
104893c04e1SHannes Petermaier /* General parts of the framework, required. */
105893c04e1SHannes Petermaier 
106893c04e1SHannes Petermaier #endif	/* ! __BUR_AM335X_COMMON_H__ */
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