xref: /rk3399_rockchip-uboot/include/configs/at91sam9x5ek.h (revision c6de2aae290151e042ec480accafecb4e77fd4fd)
1f7fa2f37SBo Shen /*
2f7fa2f37SBo Shen  * Copyright (C) 2012 Atmel Corporation
3f7fa2f37SBo Shen  *
4f7fa2f37SBo Shen  * Configuation settings for the AT91SAM9X5EK board.
5f7fa2f37SBo Shen  *
61a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
7f7fa2f37SBo Shen  */
8f7fa2f37SBo Shen 
9f7fa2f37SBo Shen #ifndef __CONFIG_H__
10f7fa2f37SBo Shen #define __CONFIG_H__
11f7fa2f37SBo Shen 
12f7fa2f37SBo Shen #include <asm/hardware.h>
13f7fa2f37SBo Shen 
1477461a65SBo Shen #define CONFIG_SYS_TEXT_BASE		0x26f00000
1577461a65SBo Shen 
16f7fa2f37SBo Shen /* ARM asynchronous clock */
17f7fa2f37SBo Shen #define CONFIG_SYS_AT91_SLOW_CLOCK	32768
18f7fa2f37SBo Shen #define CONFIG_SYS_AT91_MAIN_CLOCK	12000000	/* 12 MHz crystal */
19f7fa2f37SBo Shen 
20f7fa2f37SBo Shen #define CONFIG_AT91SAM9X5EK
21f7fa2f37SBo Shen 
22f7fa2f37SBo Shen #define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
23f7fa2f37SBo Shen #define CONFIG_SETUP_MEMORY_TAGS
24f7fa2f37SBo Shen #define CONFIG_INITRD_TAG
25f7fa2f37SBo Shen #define CONFIG_SKIP_LOWLEVEL_INIT
26f7fa2f37SBo Shen 
27f7fa2f37SBo Shen /* general purpose I/O */
28f7fa2f37SBo Shen #define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */
29f7fa2f37SBo Shen 
30f7fa2f37SBo Shen /* LCD */
31f7fa2f37SBo Shen #define LCD_BPP			LCD_COLOR16
32f7fa2f37SBo Shen #define LCD_OUTPUT_BPP		24
33f7fa2f37SBo Shen #define CONFIG_LCD_LOGO
34f7fa2f37SBo Shen #define CONFIG_LCD_INFO
35f7fa2f37SBo Shen #define CONFIG_LCD_INFO_BELOW_LOGO
36f7fa2f37SBo Shen #define CONFIG_ATMEL_HLCD
37f7fa2f37SBo Shen #define CONFIG_ATMEL_LCD_RGB565
38f7fa2f37SBo Shen 
39f7fa2f37SBo Shen 
40f7fa2f37SBo Shen /*
41f7fa2f37SBo Shen  * BOOTP options
42f7fa2f37SBo Shen  */
43f7fa2f37SBo Shen #define CONFIG_BOOTP_BOOTFILESIZE
44f7fa2f37SBo Shen #define CONFIG_BOOTP_BOOTPATH
45f7fa2f37SBo Shen #define CONFIG_BOOTP_GATEWAY
46f7fa2f37SBo Shen #define CONFIG_BOOTP_HOSTNAME
47f7fa2f37SBo Shen 
48f7fa2f37SBo Shen /*
498850c5d5STom Rini  * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0)
50b030e731SRichard Genoud  * NB: in this case, USB 1.1 devices won't be recognized.
51b030e731SRichard Genoud  */
52b030e731SRichard Genoud 
53f7fa2f37SBo Shen /* SDRAM */
54f7fa2f37SBo Shen #define CONFIG_NR_DRAM_BANKS		1
55f7fa2f37SBo Shen #define CONFIG_SYS_SDRAM_BASE		0x20000000
56f7fa2f37SBo Shen #define CONFIG_SYS_SDRAM_SIZE		0x08000000	/* 128 megs */
57f7fa2f37SBo Shen 
58f7fa2f37SBo Shen #define CONFIG_SYS_INIT_SP_ADDR \
5974631b69SWenyou Yang 	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
60f7fa2f37SBo Shen 
61f7fa2f37SBo Shen /* DataFlash */
621d7442e6SBo Shen #ifdef CONFIG_CMD_SF
631d7442e6SBo Shen #define CONFIG_SF_DEFAULT_SPEED		30000000
64f7fa2f37SBo Shen #endif
65f7fa2f37SBo Shen 
66f7fa2f37SBo Shen /* NAND flash */
67f7fa2f37SBo Shen #ifdef CONFIG_CMD_NAND
68f7fa2f37SBo Shen #define CONFIG_SYS_MAX_NAND_DEVICE	1
69f7fa2f37SBo Shen #define CONFIG_SYS_NAND_BASE		0x40000000
70f7fa2f37SBo Shen #define CONFIG_SYS_NAND_DBW_8		1
71f7fa2f37SBo Shen /* our ALE is AD21 */
72f7fa2f37SBo Shen #define CONFIG_SYS_NAND_MASK_ALE	(1 << 21)
73f7fa2f37SBo Shen /* our CLE is AD22 */
74f7fa2f37SBo Shen #define CONFIG_SYS_NAND_MASK_CLE	(1 << 22)
75f7fa2f37SBo Shen #define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PD4
76f7fa2f37SBo Shen #define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PD5
77*8f1a80e9STom Rini #endif
78*8f1a80e9STom Rini 
79b030e731SRichard Genoud /* USB */
80b030e731SRichard Genoud #ifdef CONFIG_CMD_USB
818850c5d5STom Rini #ifndef CONFIG_USB_EHCI_HCD
82dcd2f1a0SBo Shen #define CONFIG_USB_ATMEL
83dcd2f1a0SBo Shen #define CONFIG_USB_ATMEL_CLK_SEL_UPLL
84b030e731SRichard Genoud #define CONFIG_USB_OHCI_NEW
85b030e731SRichard Genoud #define CONFIG_SYS_USB_OHCI_CPU_INIT
86b030e731SRichard Genoud #define CONFIG_SYS_USB_OHCI_REGS_BASE		ATMEL_BASE_OHCI
87b030e731SRichard Genoud #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9x5"
88b030e731SRichard Genoud #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	3
89b030e731SRichard Genoud #endif
90b030e731SRichard Genoud #endif
91b030e731SRichard Genoud 
92f7fa2f37SBo Shen #define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */
93f7fa2f37SBo Shen 
94f7fa2f37SBo Shen #define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
95f7fa2f37SBo Shen #define CONFIG_SYS_MEMTEST_END		0x26e00000
96f7fa2f37SBo Shen 
97f7fa2f37SBo Shen #ifdef CONFIG_SYS_USE_NANDFLASH
98f7fa2f37SBo Shen /* bootstrap + u-boot + env + linux in nandflash */
9974631b69SWenyou Yang #define CONFIG_ENV_OFFSET		0x120000
100f7fa2f37SBo Shen #define CONFIG_ENV_OFFSET_REDUND	0x100000
101f7fa2f37SBo Shen #define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
102f7fa2f37SBo Shen #define CONFIG_BOOTCOMMAND	"nand read " \
103f7fa2f37SBo Shen 				"0x22000000 0x200000 0x300000; " \
104f7fa2f37SBo Shen 				"bootm 0x22000000"
105b7e3129eSWu, Josh #elif defined(CONFIG_SYS_USE_SPIFLASH)
1061d7442e6SBo Shen /* bootstrap + u-boot + env + linux in spi flash */
1071d7442e6SBo Shen #define CONFIG_ENV_OFFSET	0x5000
1081d7442e6SBo Shen #define CONFIG_ENV_SIZE		0x3000
1091d7442e6SBo Shen #define CONFIG_ENV_SECT_SIZE	0x1000
1101d7442e6SBo Shen #define CONFIG_ENV_SPI_MAX_HZ	30000000
1111d7442e6SBo Shen #define CONFIG_BOOTCOMMAND	"sf probe 0; " \
1121d7442e6SBo Shen 				"sf read 0x22000000 0x100000 0x300000; " \
1131d7442e6SBo Shen 				"bootm 0x22000000"
114961ffc77SBo Shen #elif defined(CONFIG_SYS_USE_DATAFLASH)
115961ffc77SBo Shen /* bootstrap + u-boot + env + linux in data flash */
116961ffc77SBo Shen #define CONFIG_ENV_OFFSET	0x4200
117961ffc77SBo Shen #define CONFIG_ENV_SIZE		0x4200
118961ffc77SBo Shen #define CONFIG_ENV_SECT_SIZE	0x210
119961ffc77SBo Shen #define CONFIG_ENV_SPI_MAX_HZ	30000000
120961ffc77SBo Shen #define CONFIG_BOOTCOMMAND	"sf probe 0; " \
121961ffc77SBo Shen 				"sf read 0x22000000 0x84000 0x294000; " \
122961ffc77SBo Shen 				"bootm 0x22000000"
123b7e3129eSWu, Josh #else /* CONFIG_SYS_USE_MMC */
124b7e3129eSWu, Josh /* bootstrap + u-boot + env + linux in mmc */
12526961772SWu, Josh #define CONFIG_ENV_SIZE		0x4000
126f7fa2f37SBo Shen #endif
127f7fa2f37SBo Shen 
128f7fa2f37SBo Shen #define CONFIG_SYS_LONGHELP
129f7fa2f37SBo Shen #define CONFIG_CMDLINE_EDITING
130f7fa2f37SBo Shen #define CONFIG_AUTO_COMPLETE
131f7fa2f37SBo Shen 
132f7fa2f37SBo Shen /*
133f7fa2f37SBo Shen  * Size of malloc() pool
134f7fa2f37SBo Shen  */
135f7fa2f37SBo Shen #define CONFIG_SYS_MALLOC_LEN		(512 * 1024 + 0x1000)
136f7fa2f37SBo Shen 
137d85e8914SBo Shen /* SPL */
138d85e8914SBo Shen #define CONFIG_SPL_FRAMEWORK
139d85e8914SBo Shen #define CONFIG_SPL_TEXT_BASE		0x300000
140d85e8914SBo Shen #define CONFIG_SPL_MAX_SIZE		0x6000
141d85e8914SBo Shen #define CONFIG_SPL_STACK		0x308000
142d85e8914SBo Shen 
143d85e8914SBo Shen #define CONFIG_SPL_BSS_START_ADDR	0x20000000
144d85e8914SBo Shen #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
145d85e8914SBo Shen #define CONFIG_SYS_SPL_MALLOC_START	0x20080000
146d85e8914SBo Shen #define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
147d85e8914SBo Shen 
148d85e8914SBo Shen #define CONFIG_SYS_MONITOR_LEN		(512 << 10)
149d85e8914SBo Shen 
150d85e8914SBo Shen #define CONFIG_SYS_MASTER_CLOCK		132096000
151d85e8914SBo Shen #define CONFIG_SYS_AT91_PLLA		0x20c73f03
152d85e8914SBo Shen #define CONFIG_SYS_MCKR			0x1301
153d85e8914SBo Shen #define CONFIG_SYS_MCKR_CSS		0x1302
154d85e8914SBo Shen 
155d85e8914SBo Shen #ifdef CONFIG_SYS_USE_MMC
156d85e8914SBo Shen #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
157d85e8914SBo Shen #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
158d85e8914SBo Shen 
159d85e8914SBo Shen #elif CONFIG_SYS_USE_NANDFLASH
160d85e8914SBo Shen #define CONFIG_SPL_NAND_DRIVERS
161d85e8914SBo Shen #define CONFIG_SPL_NAND_BASE
162d85e8914SBo Shen #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
163d85e8914SBo Shen #define CONFIG_SYS_NAND_5_ADDR_CYCLE
164d85e8914SBo Shen #define CONFIG_SYS_NAND_PAGE_SIZE	0x800
165d85e8914SBo Shen #define CONFIG_SYS_NAND_PAGE_COUNT	64
166d85e8914SBo Shen #define CONFIG_SYS_NAND_OOBSIZE		64
167d85e8914SBo Shen #define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
168d85e8914SBo Shen #define CONFIG_SYS_NAND_BAD_BLOCK_POS	0x0
169d85e8914SBo Shen 
170d85e8914SBo Shen #elif CONFIG_SYS_USE_SPIFLASH
171d85e8914SBo Shen #define CONFIG_SPL_SPI_LOAD
172d85e8914SBo Shen #define CONFIG_SYS_SPI_U_BOOT_OFFS	0x8400
173d85e8914SBo Shen 
174d85e8914SBo Shen #endif
175d85e8914SBo Shen 
176f7fa2f37SBo Shen #endif
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