12118ebb4SStelian Pop /* 22118ebb4SStelian Pop * (C) Copyright 2007-2008 32118ebb4SStelian Pop * Stelian Pop <stelian.pop@leadtechdesign.com> 42118ebb4SStelian Pop * Lead Tech Design <www.leadtechdesign.com> 52118ebb4SStelian Pop * 62118ebb4SStelian Pop * Configuation settings for the AT91SAM9RLEK board. 72118ebb4SStelian Pop * 82118ebb4SStelian Pop * See file CREDITS for list of people who contributed to this 92118ebb4SStelian Pop * project. 102118ebb4SStelian Pop * 112118ebb4SStelian Pop * This program is free software; you can redistribute it and/or 122118ebb4SStelian Pop * modify it under the terms of the GNU General Public License as 132118ebb4SStelian Pop * published by the Free Software Foundation; either version 2 of 142118ebb4SStelian Pop * the License, or (at your option) any later version. 152118ebb4SStelian Pop * 162118ebb4SStelian Pop * This program is distributed in the hope that it will be useful, 172118ebb4SStelian Pop * but WITHOUT ANY WARRANTY; without even the implied warranty of 182118ebb4SStelian Pop * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 192118ebb4SStelian Pop * GNU General Public License for more details. 202118ebb4SStelian Pop * 212118ebb4SStelian Pop * You should have received a copy of the GNU General Public License 222118ebb4SStelian Pop * along with this program; if not, write to the Free Software 232118ebb4SStelian Pop * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 242118ebb4SStelian Pop * MA 02111-1307 USA 252118ebb4SStelian Pop */ 262118ebb4SStelian Pop 272118ebb4SStelian Pop #ifndef __CONFIG_H 282118ebb4SStelian Pop #define __CONFIG_H 292118ebb4SStelian Pop 302118ebb4SStelian Pop /* ARM asynchronous clock */ 31761c70b8SStelian Pop #define AT91_CPU_NAME "AT91SAM9RL" 32*ad229a44SStelian Pop #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ 33*ad229a44SStelian Pop #define AT91_MASTER_CLOCK 100000000 /* peripheral */ 34*ad229a44SStelian Pop #define AT91_CPU_CLOCK 200000000 /* cpu */ 356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ 362118ebb4SStelian Pop 372118ebb4SStelian Pop #define AT91_SLOW_CLOCK 32768 /* slow clock */ 382118ebb4SStelian Pop 392118ebb4SStelian Pop #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ 402118ebb4SStelian Pop #define CONFIG_AT91SAM9RL 1 /* It's an Atmel AT91SAM9RL SoC*/ 412118ebb4SStelian Pop #define CONFIG_AT91SAM9RLEK 1 /* on an AT91SAM9RLEK Board */ 422118ebb4SStelian Pop #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 432118ebb4SStelian Pop 442118ebb4SStelian Pop #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 452118ebb4SStelian Pop #define CONFIG_SETUP_MEMORY_TAGS 1 462118ebb4SStelian Pop #define CONFIG_INITRD_TAG 1 472118ebb4SStelian Pop 482118ebb4SStelian Pop #define CONFIG_SKIP_LOWLEVEL_INIT 492118ebb4SStelian Pop #define CONFIG_SKIP_RELOCATE_UBOOT 502118ebb4SStelian Pop 512118ebb4SStelian Pop /* 522118ebb4SStelian Pop * Hardware drivers 532118ebb4SStelian Pop */ 542118ebb4SStelian Pop #define CONFIG_ATMEL_USART 1 552118ebb4SStelian Pop #undef CONFIG_USART0 562118ebb4SStelian Pop #undef CONFIG_USART1 572118ebb4SStelian Pop #undef CONFIG_USART2 582118ebb4SStelian Pop #define CONFIG_USART3 1 /* USART 3 is DBGU */ 592118ebb4SStelian Pop 60761c70b8SStelian Pop /* LCD */ 61761c70b8SStelian Pop #define CONFIG_LCD 1 62761c70b8SStelian Pop #define LCD_BPP LCD_COLOR8 63761c70b8SStelian Pop #define CONFIG_LCD_LOGO 1 64761c70b8SStelian Pop #undef LCD_TEST_PATTERN 65761c70b8SStelian Pop #define CONFIG_LCD_INFO 1 66761c70b8SStelian Pop #define CONFIG_LCD_INFO_BELOW_LOGO 1 676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_WHITE_ON_BLACK 1 68761c70b8SStelian Pop #define CONFIG_ATMEL_LCD 1 69761c70b8SStelian Pop #define CONFIG_ATMEL_LCD_RGB565 1 706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 71761c70b8SStelian Pop 722118ebb4SStelian Pop #define CONFIG_BOOTDELAY 3 732118ebb4SStelian Pop 742118ebb4SStelian Pop /* 752118ebb4SStelian Pop * Command line configuration. 762118ebb4SStelian Pop */ 772118ebb4SStelian Pop #include <config_cmd_default.h> 782118ebb4SStelian Pop #undef CONFIG_CMD_BDI 792118ebb4SStelian Pop #undef CONFIG_CMD_IMI 802118ebb4SStelian Pop #undef CONFIG_CMD_AUTOSCRIPT 812118ebb4SStelian Pop #undef CONFIG_CMD_FPGA 822118ebb4SStelian Pop #undef CONFIG_CMD_LOADS 832118ebb4SStelian Pop #undef CONFIG_CMD_IMLS 842118ebb4SStelian Pop #undef CONFIG_CMD_NET 852118ebb4SStelian Pop #undef CONFIG_CMD_USB 862118ebb4SStelian Pop 872118ebb4SStelian Pop #define CONFIG_CMD_NAND 1 882118ebb4SStelian Pop 892118ebb4SStelian Pop /* SDRAM */ 902118ebb4SStelian Pop #define CONFIG_NR_DRAM_BANKS 1 912118ebb4SStelian Pop #define PHYS_SDRAM 0x20000000 922118ebb4SStelian Pop #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 932118ebb4SStelian Pop 942118ebb4SStelian Pop /* DataFlash */ 952118ebb4SStelian Pop #define CONFIG_HAS_DATAFLASH 1 966d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) 976d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 986d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 992118ebb4SStelian Pop #define AT91_SPI_CLK 15000000 1002118ebb4SStelian Pop #define DATAFLASH_TCSS (0x1a << 16) 1012118ebb4SStelian Pop #define DATAFLASH_TCHS (0x1 << 24) 1022118ebb4SStelian Pop 1032118ebb4SStelian Pop /* NOR flash - not present */ 1046d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NO_FLASH 1 1052118ebb4SStelian Pop 1062118ebb4SStelian Pop /* NAND flash */ 1072118ebb4SStelian Pop #define NAND_MAX_CHIPS 1 1086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 1096d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0x40000000 1106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_DBW_8 1 1112118ebb4SStelian Pop 1122118ebb4SStelian Pop /* Ethernet - not present */ 1132118ebb4SStelian Pop 1142118ebb4SStelian Pop /* USB - not supported */ 1152118ebb4SStelian Pop 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 1172118ebb4SStelian Pop 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 1196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x23e00000 1202118ebb4SStelian Pop 1216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_USE_DATAFLASH 1 1226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #undef CONFIG_SYS_USE_NANDFLASH 1232118ebb4SStelian Pop 1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_USE_DATAFLASH 1252118ebb4SStelian Pop 1262118ebb4SStelian Pop /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 127057c849cSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_DATAFLASH 1 1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 1290e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET 0x4200 1306d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 1310e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x4200 1322118ebb4SStelian Pop #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" 1332118ebb4SStelian Pop #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 1342118ebb4SStelian Pop "root=/dev/mtdblock0 " \ 1352118ebb4SStelian Pop "mtdparts=at91_nand:-(root) "\ 1362118ebb4SStelian Pop "rw rootfstype=jffs2" 1372118ebb4SStelian Pop 1386d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #else /* CONFIG_SYS_USE_NANDFLASH */ 1392118ebb4SStelian Pop 1402118ebb4SStelian Pop /* bootstrap + u-boot + env + linux in nandflash */ 14151bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 1420e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET 0x60000 1430e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET_REDUND 0x80000 1440e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 1452118ebb4SStelian Pop #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 1462118ebb4SStelian Pop #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 1472118ebb4SStelian Pop "root=/dev/mtdblock5 " \ 1482118ebb4SStelian Pop "mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \ 1492118ebb4SStelian Pop "rw rootfstype=jffs2" 1502118ebb4SStelian Pop 1512118ebb4SStelian Pop #endif 1522118ebb4SStelian Pop 1532118ebb4SStelian Pop #define CONFIG_BAUDRATE 115200 1546d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } 1552118ebb4SStelian Pop 1566d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "U-Boot> " 1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 1596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 1606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP 1 1612118ebb4SStelian Pop #define CONFIG_CMDLINE_EDITING 1 1622118ebb4SStelian Pop 1632118ebb4SStelian Pop #define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) 1642118ebb4SStelian Pop /* 1652118ebb4SStelian Pop * Size of malloc() pool 1662118ebb4SStelian Pop */ 1676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ 1692118ebb4SStelian Pop 1702118ebb4SStelian Pop #define CONFIG_STACKSIZE (32*1024) /* regular stack */ 1712118ebb4SStelian Pop 1722118ebb4SStelian Pop #ifdef CONFIG_USE_IRQ 1732118ebb4SStelian Pop #error CONFIG_USE_IRQ not supported 1742118ebb4SStelian Pop #endif 1752118ebb4SStelian Pop 1762118ebb4SStelian Pop #endif 177