1 /* 2 * (C) Copyright 2007-2008 3 * Stelian Pop <stelian@popies.net> 4 * Lead Tech Design <www.leadtechdesign.com> 5 * 6 * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES). 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #ifndef __CONFIG_H 12 #define __CONFIG_H 13 14 #include <asm/hardware.h> 15 16 #define CONFIG_SYS_TEXT_BASE 0x73f00000 17 18 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 19 20 /* ARM asynchronous clock */ 21 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 22 #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ 23 24 #define CONFIG_AT91SAM9M10G45EK 25 26 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 27 #define CONFIG_SETUP_MEMORY_TAGS 28 #define CONFIG_INITRD_TAG 29 #define CONFIG_SKIP_LOWLEVEL_INIT 30 #define CONFIG_BOARD_EARLY_INIT_F 31 32 /* general purpose I/O */ 33 #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ 34 #define CONFIG_AT91_GPIO 35 #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ 36 37 /* serial console */ 38 #define CONFIG_ATMEL_USART 39 #define CONFIG_USART_BASE ATMEL_BASE_DBGU 40 #define CONFIG_USART_ID ATMEL_ID_SYS 41 42 /* LCD */ 43 #define LCD_BPP LCD_COLOR8 44 #define CONFIG_LCD_LOGO 45 #undef LCD_TEST_PATTERN 46 #define CONFIG_LCD_INFO 47 #define CONFIG_LCD_INFO_BELOW_LOGO 48 #define CONFIG_SYS_WHITE_ON_BLACK 49 #define CONFIG_ATMEL_LCD 50 #define CONFIG_ATMEL_LCD_RGB565 51 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 52 /* board specific(not enough SRAM) */ 53 #define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000 54 55 /* LED */ 56 #define CONFIG_AT91_LED 57 #define CONFIG_RED_LED AT91_PIN_PD31 /* this is the user1 led */ 58 #define CONFIG_GREEN_LED AT91_PIN_PD0 /* this is the user2 led */ 59 60 61 /* 62 * BOOTP options 63 */ 64 #define CONFIG_BOOTP_BOOTFILESIZE 65 #define CONFIG_BOOTP_BOOTPATH 66 #define CONFIG_BOOTP_GATEWAY 67 #define CONFIG_BOOTP_HOSTNAME 68 69 /* 70 * Command line configuration. 71 */ 72 73 /* No NOR flash */ 74 #define CONFIG_SYS_NO_FLASH 75 #define CONFIG_CMD_NAND 76 77 /* SDRAM */ 78 #define CONFIG_NR_DRAM_BANKS 1 79 #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS6 80 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 81 82 #define CONFIG_SYS_INIT_SP_ADDR \ 83 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE) 84 85 /* NAND flash */ 86 #ifdef CONFIG_CMD_NAND 87 #define CONFIG_NAND_ATMEL 88 #define CONFIG_SYS_MAX_NAND_DEVICE 1 89 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 90 #define CONFIG_SYS_NAND_DBW_8 91 /* our ALE is AD21 */ 92 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) 93 /* our CLE is AD22 */ 94 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) 95 #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 96 #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8 97 98 #endif 99 100 /* MMC */ 101 102 #ifdef CONFIG_CMD_MMC 103 #define CONFIG_MMC 104 #define CONFIG_GENERIC_MMC 105 #define CONFIG_GENERIC_ATMEL_MCI 106 #endif 107 108 #if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC) 109 #define CONFIG_DOS_PARTITION 110 #endif 111 112 /* Ethernet */ 113 #define CONFIG_MACB 114 #define CONFIG_RMII 115 #define CONFIG_NET_RETRY_COUNT 20 116 #define CONFIG_RESET_PHY_R 117 #define CONFIG_AT91_WANTS_COMMON_PHY 118 119 /* USB */ 120 #define CONFIG_USB_EHCI 121 #define CONFIG_USB_EHCI_ATMEL 122 #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 123 124 #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 125 126 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 127 #define CONFIG_SYS_MEMTEST_END 0x23e00000 128 129 #ifdef CONFIG_SYS_USE_NANDFLASH 130 /* bootstrap + u-boot + env in nandflash */ 131 #define CONFIG_ENV_IS_IN_NAND 132 #define CONFIG_ENV_OFFSET 0xc0000 133 #define CONFIG_ENV_OFFSET_REDUND 0x100000 134 #define CONFIG_ENV_SIZE 0x20000 135 136 #define CONFIG_BOOTCOMMAND \ 137 "nand read 0x70000000 0x200000 0x300000;" \ 138 "bootm 0x70000000" 139 #define CONFIG_BOOTARGS \ 140 "console=ttyS0,115200 earlyprintk " \ 141 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ 142 "256k(env),256k(env_redundant),256k(spare)," \ 143 "512k(dtb),6M(kernel)ro,-(rootfs) " \ 144 "root=/dev/mtdblock7 rw rootfstype=jffs2" 145 #elif CONFIG_SYS_USE_MMC 146 /* bootstrap + u-boot + env + linux in mmc */ 147 #define FAT_ENV_INTERFACE "mmc" 148 /* 149 * We don't specify the part number, if device 0 has partition table, it means 150 * the first partition; it no partition table, then take whole device as a 151 * FAT file system. 152 */ 153 #define FAT_ENV_DEVICE_AND_PART "0" 154 #define FAT_ENV_FILE "uboot.env" 155 #define CONFIG_ENV_IS_IN_FAT 156 #define CONFIG_FAT_WRITE 157 #define CONFIG_ENV_SIZE 0x4000 158 159 #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 160 "mtdparts=atmel_nand:" \ 161 "8M(bootstrap/uboot/kernel)ro,-(rootfs) " \ 162 "root=/dev/mmcblk0p2 rw rootwait" 163 #define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \ 164 "fatload mmc 0:1 0x72000000 zImage; " \ 165 "bootz 0x72000000 - 0x71000000" 166 #endif 167 168 #define CONFIG_BAUDRATE 115200 169 170 #define CONFIG_SYS_CBSIZE 256 171 #define CONFIG_SYS_MAXARGS 16 172 #define CONFIG_SYS_LONGHELP 173 #define CONFIG_CMDLINE_EDITING 174 #define CONFIG_AUTO_COMPLETE 175 176 /* 177 * Size of malloc() pool 178 */ 179 #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 180 181 /* Defines for SPL */ 182 #define CONFIG_SPL_FRAMEWORK 183 #define CONFIG_SPL_TEXT_BASE 0x300000 184 #define CONFIG_SPL_MAX_SIZE 0x010000 185 #define CONFIG_SPL_STACK 0x310000 186 187 #define CONFIG_SYS_MONITOR_LEN 0x80000 188 189 #ifdef CONFIG_SYS_USE_MMC 190 191 #define CONFIG_SPL_BSS_START_ADDR 0x70000000 192 #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 193 #define CONFIG_SYS_SPL_MALLOC_START 0x70080000 194 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 195 196 #define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds 197 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 198 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200 199 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 200 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 201 202 #elif CONFIG_SYS_USE_NANDFLASH 203 #define CONFIG_SPL_NAND_DRIVERS 204 #define CONFIG_SPL_NAND_BASE 205 #define CONFIG_SPL_NAND_ECC 206 #define CONFIG_SPL_NAND_SOFTECC 207 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 208 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 209 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 210 211 #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 212 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 213 #define CONFIG_SYS_NAND_PAGE_COUNT 64 214 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 215 #define CONFIG_SYS_NAND_ECCSIZE 256 216 #define CONFIG_SYS_NAND_ECCBYTES 3 217 #define CONFIG_SYS_NAND_OOBSIZE 64 218 #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ 219 48, 49, 50, 51, 52, 53, 54, 55, \ 220 56, 57, 58, 59, 60, 61, 62, 63, } 221 #endif 222 223 #define CONFIG_SPL_ATMEL_SIZE 224 #define CONFIG_SYS_MASTER_CLOCK 132096000 225 #define CONFIG_SYS_AT91_PLLA 0x20c73f03 226 #define CONFIG_SYS_MCKR 0x1301 227 #define CONFIG_SYS_MCKR_CSS 0x1302 228 229 #endif 230