xref: /rk3399_rockchip-uboot/include/configs/at91sam9261ek.h (revision 4758ebdd53571d4d183be5c2db8f0ee4ef368915)
1d99a8ff6SStelian Pop /*
2d99a8ff6SStelian Pop  * (C) Copyright 2007-2008
3d99a8ff6SStelian Pop  * Stelian Pop <stelian.pop@leadtechdesign.com>
4d99a8ff6SStelian Pop  * Lead Tech Design <www.leadtechdesign.com>
5d99a8ff6SStelian Pop  *
6d99a8ff6SStelian Pop  * Configuation settings for the AT91SAM9261EK board.
7d99a8ff6SStelian Pop  *
8d99a8ff6SStelian Pop  * See file CREDITS for list of people who contributed to this
9d99a8ff6SStelian Pop  * project.
10d99a8ff6SStelian Pop  *
11d99a8ff6SStelian Pop  * This program is free software; you can redistribute it and/or
12d99a8ff6SStelian Pop  * modify it under the terms of the GNU General Public License as
13d99a8ff6SStelian Pop  * published by the Free Software Foundation; either version 2 of
14d99a8ff6SStelian Pop  * the License, or (at your option) any later version.
15d99a8ff6SStelian Pop  *
16d99a8ff6SStelian Pop  * This program is distributed in the hope that it will be useful,
17d99a8ff6SStelian Pop  * but WITHOUT ANY WARRANTY; without even the implied warranty of
18d99a8ff6SStelian Pop  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19d99a8ff6SStelian Pop  * GNU General Public License for more details.
20d99a8ff6SStelian Pop  *
21d99a8ff6SStelian Pop  * You should have received a copy of the GNU General Public License
22d99a8ff6SStelian Pop  * along with this program; if not, write to the Free Software
23d99a8ff6SStelian Pop  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24d99a8ff6SStelian Pop  * MA 02111-1307 USA
25d99a8ff6SStelian Pop  */
26d99a8ff6SStelian Pop 
27d99a8ff6SStelian Pop #ifndef __CONFIG_H
28d99a8ff6SStelian Pop #define __CONFIG_H
29d99a8ff6SStelian Pop 
30d99a8ff6SStelian Pop /* ARM asynchronous clock */
31820f2a95SStelian Pop #define AT91_CPU_NAME		"AT91SAM9261"
32ad229a44SStelian Pop #define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
33ad229a44SStelian Pop #define AT91_MASTER_CLOCK	100000000	/* peripheral */
34ad229a44SStelian Pop #define AT91_CPU_CLOCK		200000000	/* cpu */
356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ		1000000		/* 1us resolution */
36d99a8ff6SStelian Pop 
37d99a8ff6SStelian Pop #define AT91_SLOW_CLOCK		32768	/* slow clock */
38d99a8ff6SStelian Pop 
39d99a8ff6SStelian Pop #define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
40d99a8ff6SStelian Pop #define CONFIG_AT91SAM9261	1	/* It's an Atmel AT91SAM9261 SoC*/
41d99a8ff6SStelian Pop #define CONFIG_AT91SAM9261EK	1	/* on an AT91SAM9261EK Board	*/
42d99a8ff6SStelian Pop #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
43d99a8ff6SStelian Pop 
44d99a8ff6SStelian Pop #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
45d99a8ff6SStelian Pop #define CONFIG_SETUP_MEMORY_TAGS 1
46d99a8ff6SStelian Pop #define CONFIG_INITRD_TAG	1
47d99a8ff6SStelian Pop 
48d99a8ff6SStelian Pop #define CONFIG_SKIP_LOWLEVEL_INIT
49d99a8ff6SStelian Pop #define CONFIG_SKIP_RELOCATE_UBOOT
50d99a8ff6SStelian Pop 
51d99a8ff6SStelian Pop /*
52d99a8ff6SStelian Pop  * Hardware drivers
53d99a8ff6SStelian Pop  */
54d99a8ff6SStelian Pop #define CONFIG_ATMEL_USART	1
55d99a8ff6SStelian Pop #undef CONFIG_USART0
56d99a8ff6SStelian Pop #undef CONFIG_USART1
57d99a8ff6SStelian Pop #undef CONFIG_USART2
58d99a8ff6SStelian Pop #define CONFIG_USART3		1	/* USART 3 is DBGU */
59d99a8ff6SStelian Pop 
60820f2a95SStelian Pop /* LCD */
61820f2a95SStelian Pop #define CONFIG_LCD			1
62820f2a95SStelian Pop #define LCD_BPP				LCD_COLOR8
63820f2a95SStelian Pop #define CONFIG_LCD_LOGO			1
64820f2a95SStelian Pop #undef LCD_TEST_PATTERN
65820f2a95SStelian Pop #define CONFIG_LCD_INFO			1
66820f2a95SStelian Pop #define CONFIG_LCD_INFO_BELOW_LOGO	1
676d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_WHITE_ON_BLACK		1
68820f2a95SStelian Pop #define CONFIG_ATMEL_LCD		1
69820f2a95SStelian Pop #define CONFIG_ATMEL_LCD_BGR555		1
706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
71820f2a95SStelian Pop 
72a484b00bSJean-Christophe PLAGNIOL-VILLARD /* LED */
73a484b00bSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_AT91_LED
74a484b00bSJean-Christophe PLAGNIOL-VILLARD #define	CONFIG_RED_LED		AT91_PIN_PA23	/* this is the power led */
75a484b00bSJean-Christophe PLAGNIOL-VILLARD #define	CONFIG_GREEN_LED	AT91_PIN_PA13	/* this is the user1 led */
76a484b00bSJean-Christophe PLAGNIOL-VILLARD #define	CONFIG_YELLOW_LED	AT91_PIN_PA14	/* this is the user2 led */
77a484b00bSJean-Christophe PLAGNIOL-VILLARD 
78d99a8ff6SStelian Pop #define CONFIG_BOOTDELAY	3
79d99a8ff6SStelian Pop 
80d99a8ff6SStelian Pop /*
81d99a8ff6SStelian Pop  * BOOTP options
82d99a8ff6SStelian Pop  */
83d99a8ff6SStelian Pop #define CONFIG_BOOTP_BOOTFILESIZE	1
84d99a8ff6SStelian Pop #define CONFIG_BOOTP_BOOTPATH		1
85d99a8ff6SStelian Pop #define CONFIG_BOOTP_GATEWAY		1
86d99a8ff6SStelian Pop #define CONFIG_BOOTP_HOSTNAME		1
87d99a8ff6SStelian Pop 
88d99a8ff6SStelian Pop /*
89d99a8ff6SStelian Pop  * Command line configuration.
90d99a8ff6SStelian Pop  */
91d99a8ff6SStelian Pop #include <config_cmd_default.h>
92d99a8ff6SStelian Pop #undef CONFIG_CMD_BDI
93d99a8ff6SStelian Pop #undef CONFIG_CMD_FPGA
9474de7aefSWolfgang Denk #undef CONFIG_CMD_IMI
95d99a8ff6SStelian Pop #undef CONFIG_CMD_IMLS
9674de7aefSWolfgang Denk #undef CONFIG_CMD_LOADS
9774de7aefSWolfgang Denk #undef CONFIG_CMD_SOURCE
98d99a8ff6SStelian Pop 
99d99a8ff6SStelian Pop #define CONFIG_CMD_PING		1
100d99a8ff6SStelian Pop #define CONFIG_CMD_DHCP		1
101d99a8ff6SStelian Pop #define CONFIG_CMD_NAND		1
102d99a8ff6SStelian Pop #define CONFIG_CMD_USB		1
103d99a8ff6SStelian Pop 
104d99a8ff6SStelian Pop /* SDRAM */
105d99a8ff6SStelian Pop #define CONFIG_NR_DRAM_BANKS		1
106d99a8ff6SStelian Pop #define PHYS_SDRAM			0x20000000
107d99a8ff6SStelian Pop #define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */
108d99a8ff6SStelian Pop 
109d99a8ff6SStelian Pop /* DataFlash */
110*4758ebddSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ATMEL_DATAFLASH_SPI
111d99a8ff6SStelian Pop #define CONFIG_HAS_DATAFLASH		1
1126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
1136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
1146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
1156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */
116d99a8ff6SStelian Pop #define AT91_SPI_CLK			15000000
117d99a8ff6SStelian Pop #define DATAFLASH_TCSS			(0x1a << 16)
118d99a8ff6SStelian Pop #define DATAFLASH_TCHS			(0x1 << 24)
119d99a8ff6SStelian Pop 
120d99a8ff6SStelian Pop /* NAND flash */
12174c076d6SJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_CMD_NAND
12274c076d6SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_NAND_ATMEL
1236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE		1
1246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE			0x40000000
1256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_DBW_8			1
12674c076d6SJean-Christophe PLAGNIOL-VILLARD /* our ALE is AD22 */
12774c076d6SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
12874c076d6SJean-Christophe PLAGNIOL-VILLARD /* our CLE is AD21 */
12974c076d6SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
13074c076d6SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
13174c076d6SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC15
13274c076d6SJean-Christophe PLAGNIOL-VILLARD #endif
133d99a8ff6SStelian Pop 
134d99a8ff6SStelian Pop /* NOR flash - no real flash on this board */
1356d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NO_FLASH			1
136d99a8ff6SStelian Pop 
137d99a8ff6SStelian Pop /* Ethernet */
138d99a8ff6SStelian Pop #define CONFIG_DRIVER_DM9000		1
139d99a8ff6SStelian Pop #define CONFIG_DM9000_BASE		0x30000000
140d99a8ff6SStelian Pop #define DM9000_IO			CONFIG_DM9000_BASE
141d99a8ff6SStelian Pop #define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
142d99a8ff6SStelian Pop #define CONFIG_DM9000_USE_16BIT		1
143d99a8ff6SStelian Pop #define CONFIG_NET_RETRY_COUNT		20
144d99a8ff6SStelian Pop #define CONFIG_RESET_PHY_R		1
145d99a8ff6SStelian Pop 
146d99a8ff6SStelian Pop /* USB */
1472b7178afSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_USB_ATMEL
148d99a8ff6SStelian Pop #define CONFIG_USB_OHCI_NEW		1
149d99a8ff6SStelian Pop #define CONFIG_DOS_PARTITION		1
1506d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
1516d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9261_UHP_BASE */
1526d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
1536d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
154d99a8ff6SStelian Pop #define CONFIG_USB_STORAGE		1
1553e0cda07SStelian Pop #define CONFIG_CMD_FAT			1
156d99a8ff6SStelian Pop 
1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */
158d99a8ff6SStelian Pop 
1596d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
1606d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END			0x23e00000
161d99a8ff6SStelian Pop 
1626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_USE_DATAFLASH_CS0
163d99a8ff6SStelian Pop 
164d99a8ff6SStelian Pop /* bootstrap + u-boot + env + linux in dataflash on CS0 */
165057c849cSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_DATAFLASH	1
1666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
1670e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET	0x4200
1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
1690e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE		0x4200
170d99a8ff6SStelian Pop #define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
171d99a8ff6SStelian Pop #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
172d99a8ff6SStelian Pop 				"root=/dev/mtdblock0 "			\
173d99a8ff6SStelian Pop 				"mtdparts=at91_nand:-(root) "		\
174d99a8ff6SStelian Pop 				"rw rootfstype=jffs2"
175d99a8ff6SStelian Pop 
17689a7a87fSNicolas Ferre #elif CONFIG_SYS_USE_DATAFLASH_CS3
17789a7a87fSNicolas Ferre 
17889a7a87fSNicolas Ferre /* bootstrap + u-boot + env + linux in dataflash on CS3 */
17989a7a87fSNicolas Ferre #define CONFIG_ENV_IS_IN_DATAFLASH	1
18089a7a87fSNicolas Ferre #define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400)
18189a7a87fSNicolas Ferre #define CONFIG_ENV_OFFSET	0x4200
18289a7a87fSNicolas Ferre #define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET)
18389a7a87fSNicolas Ferre #define CONFIG_ENV_SIZE		0x4200
18489a7a87fSNicolas Ferre #define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
18589a7a87fSNicolas Ferre #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
18689a7a87fSNicolas Ferre 				"root=/dev/mtdblock0 "			\
18789a7a87fSNicolas Ferre 				"mtdparts=at91_nand:-(root) "		\
18889a7a87fSNicolas Ferre 				"rw rootfstype=jffs2"
18989a7a87fSNicolas Ferre 
1906d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #else /* CONFIG_SYS_USE_NANDFLASH */
191d99a8ff6SStelian Pop 
192d99a8ff6SStelian Pop /* bootstrap + u-boot + env + linux in nandflash */
19351bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND	1
1940e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET		0x60000
1950e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET_REDUND	0x80000
1960e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
197d99a8ff6SStelian Pop #define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
198d99a8ff6SStelian Pop #define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
199d99a8ff6SStelian Pop 				"root=/dev/mtdblock5 "			\
200d99a8ff6SStelian Pop 				"mtdparts=at91_nand:128k(bootstrap)ro,"	\
201d99a8ff6SStelian Pop 				"256k(uboot)ro,128k(env1)ro,"		\
202d99a8ff6SStelian Pop 				"128k(env2)ro,2M(linux),-(root) "	\
203d99a8ff6SStelian Pop 				"rw rootfstype=jffs2"
204d99a8ff6SStelian Pop 
205d99a8ff6SStelian Pop #endif
206d99a8ff6SStelian Pop 
207d99a8ff6SStelian Pop #define CONFIG_BAUDRATE		115200
2086d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
209d99a8ff6SStelian Pop 
2106d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT		"U-Boot> "
2116d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE		256
2126d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS		16
2136d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
2146d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP		1
215d99a8ff6SStelian Pop #define CONFIG_CMDLINE_EDITING	1
216d99a8ff6SStelian Pop 
217d99a8ff6SStelian Pop #define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
218d99a8ff6SStelian Pop /*
219d99a8ff6SStelian Pop  * Size of malloc() pool
220d99a8ff6SStelian Pop  */
2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
223d99a8ff6SStelian Pop 
224d99a8ff6SStelian Pop #define CONFIG_STACKSIZE	(32*1024)	/* regular stack */
225d99a8ff6SStelian Pop 
226d99a8ff6SStelian Pop #ifdef CONFIG_USE_IRQ
227d99a8ff6SStelian Pop #error CONFIG_USE_IRQ not supported
228d99a8ff6SStelian Pop #endif
229d99a8ff6SStelian Pop 
230d99a8ff6SStelian Pop #endif
231