1d99a8ff6SStelian Pop /* 2d99a8ff6SStelian Pop * (C) Copyright 2007-2008 3d99a8ff6SStelian Pop * Stelian Pop <stelian.pop@leadtechdesign.com> 4d99a8ff6SStelian Pop * Lead Tech Design <www.leadtechdesign.com> 5d99a8ff6SStelian Pop * 6d99a8ff6SStelian Pop * Configuation settings for the AT91SAM9261EK board. 7d99a8ff6SStelian Pop * 8d99a8ff6SStelian Pop * See file CREDITS for list of people who contributed to this 9d99a8ff6SStelian Pop * project. 10d99a8ff6SStelian Pop * 11d99a8ff6SStelian Pop * This program is free software; you can redistribute it and/or 12d99a8ff6SStelian Pop * modify it under the terms of the GNU General Public License as 13d99a8ff6SStelian Pop * published by the Free Software Foundation; either version 2 of 14d99a8ff6SStelian Pop * the License, or (at your option) any later version. 15d99a8ff6SStelian Pop * 16d99a8ff6SStelian Pop * This program is distributed in the hope that it will be useful, 17d99a8ff6SStelian Pop * but WITHOUT ANY WARRANTY; without even the implied warranty of 18d99a8ff6SStelian Pop * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19d99a8ff6SStelian Pop * GNU General Public License for more details. 20d99a8ff6SStelian Pop * 21d99a8ff6SStelian Pop * You should have received a copy of the GNU General Public License 22d99a8ff6SStelian Pop * along with this program; if not, write to the Free Software 23d99a8ff6SStelian Pop * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24d99a8ff6SStelian Pop * MA 02111-1307 USA 25d99a8ff6SStelian Pop */ 26d99a8ff6SStelian Pop 27d99a8ff6SStelian Pop #ifndef __CONFIG_H 28d99a8ff6SStelian Pop #define __CONFIG_H 29d99a8ff6SStelian Pop 30d99a8ff6SStelian Pop /* ARM asynchronous clock */ 31ad229a44SStelian Pop #define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ 326ebff365SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_HZ 1000 33d99a8ff6SStelian Pop 34d99a8ff6SStelian Pop #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ 355ccc2d99SSedji Gaouaou #ifdef CONFIG_AT91SAM9G10EK 365ccc2d99SSedji Gaouaou #define CONFIG_AT91SAM9G10 1 /* It's an Atmel AT91SAM9G10 SoC*/ 375ccc2d99SSedji Gaouaou #else 38d99a8ff6SStelian Pop #define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/ 395ccc2d99SSedji Gaouaou #endif 40dc39ae95SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ARCH_CPU_INIT 41d99a8ff6SStelian Pop #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 42d99a8ff6SStelian Pop 43d99a8ff6SStelian Pop #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 44d99a8ff6SStelian Pop #define CONFIG_SETUP_MEMORY_TAGS 1 45d99a8ff6SStelian Pop #define CONFIG_INITRD_TAG 1 46d99a8ff6SStelian Pop 47d99a8ff6SStelian Pop #define CONFIG_SKIP_LOWLEVEL_INIT 48d99a8ff6SStelian Pop #define CONFIG_SKIP_RELOCATE_UBOOT 49d99a8ff6SStelian Pop 50d99a8ff6SStelian Pop /* 51d99a8ff6SStelian Pop * Hardware drivers 52d99a8ff6SStelian Pop */ 53d99a8ff6SStelian Pop #define CONFIG_ATMEL_USART 1 54d99a8ff6SStelian Pop #undef CONFIG_USART0 55d99a8ff6SStelian Pop #undef CONFIG_USART1 56d99a8ff6SStelian Pop #undef CONFIG_USART2 57d99a8ff6SStelian Pop #define CONFIG_USART3 1 /* USART 3 is DBGU */ 58d99a8ff6SStelian Pop 59820f2a95SStelian Pop /* LCD */ 60820f2a95SStelian Pop #define CONFIG_LCD 1 61820f2a95SStelian Pop #define LCD_BPP LCD_COLOR8 62820f2a95SStelian Pop #define CONFIG_LCD_LOGO 1 63820f2a95SStelian Pop #undef LCD_TEST_PATTERN 64820f2a95SStelian Pop #define CONFIG_LCD_INFO 1 65820f2a95SStelian Pop #define CONFIG_LCD_INFO_BELOW_LOGO 1 666d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_WHITE_ON_BLACK 1 67820f2a95SStelian Pop #define CONFIG_ATMEL_LCD 1 685ccc2d99SSedji Gaouaou #ifdef CONFIG_AT91SAM9261EK 69820f2a95SStelian Pop #define CONFIG_ATMEL_LCD_BGR555 1 705ccc2d99SSedji Gaouaou #else 715ccc2d99SSedji Gaouaou #define CONFIG_AT91SAM9G10_LCD_BASE 0x23E00000 /* LCD is no more in SRAM */ 725ccc2d99SSedji Gaouaou #endif 736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 74820f2a95SStelian Pop 75a484b00bSJean-Christophe PLAGNIOL-VILLARD /* LED */ 76a484b00bSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_AT91_LED 77a484b00bSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_RED_LED AT91_PIN_PA23 /* this is the power led */ 78a484b00bSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_GREEN_LED AT91_PIN_PA13 /* this is the user1 led */ 79a484b00bSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_YELLOW_LED AT91_PIN_PA14 /* this is the user2 led */ 80a484b00bSJean-Christophe PLAGNIOL-VILLARD 81d99a8ff6SStelian Pop #define CONFIG_BOOTDELAY 3 82d99a8ff6SStelian Pop 83d99a8ff6SStelian Pop /* 84d99a8ff6SStelian Pop * BOOTP options 85d99a8ff6SStelian Pop */ 86d99a8ff6SStelian Pop #define CONFIG_BOOTP_BOOTFILESIZE 1 87d99a8ff6SStelian Pop #define CONFIG_BOOTP_BOOTPATH 1 88d99a8ff6SStelian Pop #define CONFIG_BOOTP_GATEWAY 1 89d99a8ff6SStelian Pop #define CONFIG_BOOTP_HOSTNAME 1 90d99a8ff6SStelian Pop 91d99a8ff6SStelian Pop /* 92d99a8ff6SStelian Pop * Command line configuration. 93d99a8ff6SStelian Pop */ 94d99a8ff6SStelian Pop #include <config_cmd_default.h> 95d99a8ff6SStelian Pop #undef CONFIG_CMD_BDI 96d99a8ff6SStelian Pop #undef CONFIG_CMD_FPGA 9774de7aefSWolfgang Denk #undef CONFIG_CMD_IMI 98d99a8ff6SStelian Pop #undef CONFIG_CMD_IMLS 9974de7aefSWolfgang Denk #undef CONFIG_CMD_LOADS 10074de7aefSWolfgang Denk #undef CONFIG_CMD_SOURCE 101d99a8ff6SStelian Pop 102d99a8ff6SStelian Pop #define CONFIG_CMD_PING 1 103d99a8ff6SStelian Pop #define CONFIG_CMD_DHCP 1 104d99a8ff6SStelian Pop #define CONFIG_CMD_NAND 1 105d99a8ff6SStelian Pop #define CONFIG_CMD_USB 1 106d99a8ff6SStelian Pop 107d99a8ff6SStelian Pop /* SDRAM */ 108d99a8ff6SStelian Pop #define CONFIG_NR_DRAM_BANKS 1 109d99a8ff6SStelian Pop #define PHYS_SDRAM 0x20000000 110d99a8ff6SStelian Pop #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ 111d99a8ff6SStelian Pop 112d99a8ff6SStelian Pop /* DataFlash */ 1134758ebddSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ATMEL_DATAFLASH_SPI 114d99a8ff6SStelian Pop #define CONFIG_HAS_DATAFLASH 1 1156d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) 1166d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_DATAFLASH_BANKS 2 1176d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ 1186d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */ 119d99a8ff6SStelian Pop #define AT91_SPI_CLK 15000000 120d99a8ff6SStelian Pop #define DATAFLASH_TCSS (0x1a << 16) 121d99a8ff6SStelian Pop #define DATAFLASH_TCHS (0x1 << 24) 122d99a8ff6SStelian Pop 123d99a8ff6SStelian Pop /* NAND flash */ 12474c076d6SJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_CMD_NAND 12574c076d6SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_NAND_ATMEL 1266d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAX_NAND_DEVICE 1 1276d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_BASE 0x40000000 1286d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_DBW_8 1 12974c076d6SJean-Christophe PLAGNIOL-VILLARD /* our ALE is AD22 */ 13074c076d6SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) 13174c076d6SJean-Christophe PLAGNIOL-VILLARD /* our CLE is AD21 */ 13274c076d6SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) 13374c076d6SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 13474c076d6SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15 135*2eb99ca8SWolfgang Denk 136*2eb99ca8SWolfgang Denk #define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ 13774c076d6SJean-Christophe PLAGNIOL-VILLARD #endif 138d99a8ff6SStelian Pop 139d99a8ff6SStelian Pop /* NOR flash - no real flash on this board */ 1406d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_NO_FLASH 1 141d99a8ff6SStelian Pop 142d99a8ff6SStelian Pop /* Ethernet */ 14360f61e6dSRemy Bohmer #define CONFIG_NET_MULTI 1 144d99a8ff6SStelian Pop #define CONFIG_DRIVER_DM9000 1 145d99a8ff6SStelian Pop #define CONFIG_DM9000_BASE 0x30000000 146d99a8ff6SStelian Pop #define DM9000_IO CONFIG_DM9000_BASE 147d99a8ff6SStelian Pop #define DM9000_DATA (CONFIG_DM9000_BASE + 4) 148d99a8ff6SStelian Pop #define CONFIG_DM9000_USE_16BIT 1 149e5a3bc24SRemy Bohmer #define CONFIG_DM9000_NO_SROM 1 150d99a8ff6SStelian Pop #define CONFIG_NET_RETRY_COUNT 20 151d99a8ff6SStelian Pop #define CONFIG_RESET_PHY_R 1 152d99a8ff6SStelian Pop 153d99a8ff6SStelian Pop /* USB */ 1542b7178afSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_USB_ATMEL 155d99a8ff6SStelian Pop #define CONFIG_USB_OHCI_NEW 1 156d99a8ff6SStelian Pop #define CONFIG_DOS_PARTITION 1 1576d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 1586d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ 1595ccc2d99SSedji Gaouaou #ifdef CONFIG_AT91SAM9G10EK 1605ccc2d99SSedji Gaouaou #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" 1615ccc2d99SSedji Gaouaou #else 1626d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" 1635ccc2d99SSedji Gaouaou #endif 1646d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 165d99a8ff6SStelian Pop #define CONFIG_USB_STORAGE 1 1663e0cda07SStelian Pop #define CONFIG_CMD_FAT 1 167d99a8ff6SStelian Pop 1686d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ 169d99a8ff6SStelian Pop 1706d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 1716d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MEMTEST_END 0x23e00000 172d99a8ff6SStelian Pop 1736d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 174d99a8ff6SStelian Pop 175d99a8ff6SStelian Pop /* bootstrap + u-boot + env + linux in dataflash on CS0 */ 176057c849cSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_DATAFLASH 1 1776d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) 1780e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET 0x4200 1796d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) 1800e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x4200 181d99a8ff6SStelian Pop #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" 182d99a8ff6SStelian Pop #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 183d99a8ff6SStelian Pop "root=/dev/mtdblock0 " \ 184d99a8ff6SStelian Pop "mtdparts=at91_nand:-(root) " \ 185d99a8ff6SStelian Pop "rw rootfstype=jffs2" 186d99a8ff6SStelian Pop 18789a7a87fSNicolas Ferre #elif CONFIG_SYS_USE_DATAFLASH_CS3 18889a7a87fSNicolas Ferre 18989a7a87fSNicolas Ferre /* bootstrap + u-boot + env + linux in dataflash on CS3 */ 19089a7a87fSNicolas Ferre #define CONFIG_ENV_IS_IN_DATAFLASH 1 19189a7a87fSNicolas Ferre #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + 0x8400) 19289a7a87fSNicolas Ferre #define CONFIG_ENV_OFFSET 0x4200 19389a7a87fSNicolas Ferre #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 + CONFIG_ENV_OFFSET) 19489a7a87fSNicolas Ferre #define CONFIG_ENV_SIZE 0x4200 19589a7a87fSNicolas Ferre #define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm" 19689a7a87fSNicolas Ferre #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 19789a7a87fSNicolas Ferre "root=/dev/mtdblock0 " \ 19889a7a87fSNicolas Ferre "mtdparts=at91_nand:-(root) " \ 19989a7a87fSNicolas Ferre "rw rootfstype=jffs2" 20089a7a87fSNicolas Ferre 2016d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #else /* CONFIG_SYS_USE_NANDFLASH */ 202d99a8ff6SStelian Pop 203d99a8ff6SStelian Pop /* bootstrap + u-boot + env + linux in nandflash */ 20451bfee19SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_IS_IN_NAND 1 2050e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET 0x60000 2060e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_OFFSET_REDUND 0x80000 2070e8d1586SJean-Christophe PLAGNIOL-VILLARD #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ 208d99a8ff6SStelian Pop #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" 209d99a8ff6SStelian Pop #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ 210d99a8ff6SStelian Pop "root=/dev/mtdblock5 " \ 211d99a8ff6SStelian Pop "mtdparts=at91_nand:128k(bootstrap)ro," \ 212d99a8ff6SStelian Pop "256k(uboot)ro,128k(env1)ro," \ 213d99a8ff6SStelian Pop "128k(env2)ro,2M(linux),-(root) " \ 214d99a8ff6SStelian Pop "rw rootfstype=jffs2" 215d99a8ff6SStelian Pop 216d99a8ff6SStelian Pop #endif 217d99a8ff6SStelian Pop 218d99a8ff6SStelian Pop #define CONFIG_BAUDRATE 115200 2196d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } 220d99a8ff6SStelian Pop 2216d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PROMPT "U-Boot> " 2226d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_CBSIZE 256 2236d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MAXARGS 16 2246d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 2256d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_LONGHELP 1 226d99a8ff6SStelian Pop #define CONFIG_CMDLINE_EDITING 1 227d99a8ff6SStelian Pop 228d99a8ff6SStelian Pop #define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) 229d99a8ff6SStelian Pop /* 230d99a8ff6SStelian Pop * Size of malloc() pool 231d99a8ff6SStelian Pop */ 2326d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) 2336d0f6bcfSJean-Christophe PLAGNIOL-VILLARD #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ 234d99a8ff6SStelian Pop 235d99a8ff6SStelian Pop #define CONFIG_STACKSIZE (32*1024) /* regular stack */ 236d99a8ff6SStelian Pop 237d99a8ff6SStelian Pop #ifdef CONFIG_USE_IRQ 238d99a8ff6SStelian Pop #error CONFIG_USE_IRQ not supported 239d99a8ff6SStelian Pop #endif 240d99a8ff6SStelian Pop 241d99a8ff6SStelian Pop #endif 242