xref: /rk3399_rockchip-uboot/include/configs/at91rm9200ek.h (revision cb82a532669f6b02225ec3429ea4d49ff2b97d0a)
1 /*
2  * Ulf Samuelsson <ulf@atmel.com>
3  * Rick Bronson <rick@efn.org>
4  *
5  * Configuration settings for the AT91RM9200EK board.
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25 
26 #ifndef __CONFIG_H
27 #define __CONFIG_H
28 
29 /* ARM asynchronous clock */
30 /*
31  * from 18.432 MHz crystal
32  * (18432000 / 4 * 39)
33  */
34 #define AT91C_MAIN_CLOCK	179712000
35 /*
36  * peripheral clock
37  * (AT91C_MASTER_CLOCK / 3)
38  */
39 #define AT91C_MASTER_CLOCK	59904000
40 
41 #define AT91_SLOW_CLOCK		32768	/* slow clock */
42 
43 #define CONFIG_ARM920T		1	/* This is an ARM920T Core	*/
44 #define CONFIG_AT91RM9200	1	/* It's an Atmel AT91RM9200 SoC	*/
45 #define CONFIG_AT91RM9200EK	1	/* on an AT91RM9200EK Board	*/
46 #undef  CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/
47 #define USE_920T_MMU		1
48 
49 #define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
50 #define CONFIG_SETUP_MEMORY_TAGS 1
51 #define CONFIG_INITRD_TAG	1
52 
53 /*
54  * LowLevel Init
55  */
56 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
57 #define CONFIG_SYS_USE_MAIN_OSCILLATOR		1
58 /* flash */
59 #define CONFIG_SYS_MC_PUIA_VAL	0x00000000
60 #define CONFIG_SYS_MC_PUP_VAL	0x00000000
61 #define CONFIG_SYS_MC_PUER_VAL	0x00000000
62 #define CONFIG_SYS_MC_ASR_VAL	0x00000000
63 #define CONFIG_SYS_MC_AASR_VAL	0x00000000
64 #define CONFIG_SYS_EBI_CFGR_VAL	0x00000000
65 #define CONFIG_SYS_SMC_CSR0_VAL	0x00003284 /* 16bit, 2 TDF, 4 WS */
66 
67 /* clocks */
68 #define CONFIG_SYS_PLLAR_VAL	0x20263E04 /* 179.712000 MHz for PCK */
69 #define CONFIG_SYS_PLLBR_VAL	0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
70 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
71 #define CONFIG_SYS_MCKR_VAL	0x00000202
72 
73 /* sdram */
74 #define CONFIG_SYS_PIOC_ASR_VAL	0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
75 #define CONFIG_SYS_PIOC_BSR_VAL	0x00000000
76 #define CONFIG_SYS_PIOC_PDR_VAL	0xFFFF0000
77 #define CONFIG_SYS_EBI_CSA_VAL	0x00000002 /* CS1=CONFIG_SYS_SDRAM */
78 #define CONFIG_SYS_SDRC_CR_VAL	0x2188c155 /* set up the CONFIG_SYS_SDRAM */
79 #define CONFIG_SYS_SDRAM	0x20000000 /* address of the CONFIG_SYS_SDRAM */
80 #define CONFIG_SYS_SDRAM1	0x20000080 /* address of the CONFIG_SYS_SDRAM */
81 #define CONFIG_SYS_SDRAM_VAL	0x00000000 /* value written to CONFIG_SYS_SDRAM */
82 #define CONFIG_SYS_SDRC_MR_VAL	0x00000002 /* Precharge All */
83 #define CONFIG_SYS_SDRC_MR_VAL1	0x00000004 /* refresh */
84 #define CONFIG_SYS_SDRC_MR_VAL2	0x00000003 /* Load Mode Register */
85 #define CONFIG_SYS_SDRC_MR_VAL3	0x00000000 /* Normal Mode */
86 #define CONFIG_SYS_SDRC_TR_VAL	0x000002E0 /* Write refresh rate */
87 #else
88 #define CONFIG_SKIP_RELOCATE_UBOOT
89 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
90 
91 /* hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
92 #define CONFIG_SYS_AT91C_BRGR_DIVISOR	33
93 
94 /*
95  * Memory Configuration
96  */
97 #define CONFIG_NR_DRAM_BANKS		1
98 #define PHYS_SDRAM			0x20000000
99 #define PHYS_SDRAM_SIZE			0x02000000	/* 32 megs */
100 
101 #define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM
102 #define CONFIG_SYS_MEMTEST_END		\
103 		(CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144)
104 
105 /*
106  * Hardware drivers
107  */
108 
109 /*
110  * UART Configuration
111  *
112  * define one of these to choose the DBGU,
113  * USART0 or USART1 as console
114  */
115 #define CONFIG_DBGU
116 #undef CONFIG_USART0
117 #undef CONFIG_USART1
118 /* don't include RTS/CTS flow control support	*/
119 #undef	CONFIG_HWFLOW
120 /* disable modem initialization stuff */
121 #undef	CONFIG_MODEM_SUPPORT
122 
123 #define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
124 #define CONFIG_BAUDRATE			115200
125 
126 /*
127  * Command line configuration.
128  */
129 #include <config_cmd_default.h>
130 
131 #define CONFIG_CMD_DHCP
132 #define CONFIG_CMD_FAT
133 #define CONFIG_CMD_MII
134 #define CONFIG_CMD_PING
135 
136 #undef CONFIG_CMD_BDI
137 #undef CONFIG_CMD_IMI
138 #undef CONFIG_CMD_FPGA
139 #undef CONFIG_CMD_MISC
140 #undef CONFIG_CMD_LOADS
141 
142 #include <asm/arch/AT91RM9200.h>	/* needed for port definitions */
143 /* Options for MMC/SD Card */
144 #define CONFIG_DOS_PARTITION	1
145 #undef CONFIG_MMC
146 #define CONFIG_SYS_MMC_BASE		0xFFFB4000
147 #define CONFIG_SYS_MMC_BLOCKSIZE	512
148 
149 /*
150  * Network Driver Setting
151  */
152 #define CONFIG_DRIVER_ETHER
153 #define CONFIG_NET_RETRY_COUNT		20
154 #define CONFIG_AT91C_USE_RMII
155 
156 /*
157  * AC Characteristics
158  * DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns
159  */
160 #define DATAFLASH_TCSS	(0xC << 16)
161 #define DATAFLASH_TCHS	(0x1 << 24)
162 
163 #if defined(CONFIG_HAS_DATAFLASH)
164 #define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
165 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
166 #define CONFIG_SYS_MAX_DATAFLASH_PAGES		16384
167 /* Logical adress for CS0 */
168 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000
169 /* Logical adress for CS3 */
170 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000
171 #define	CONFIG_SYS_SUPPORT_BLOCK_ERASE		1
172 #define	CONFIG_SYS_DATAFLASH_MMC_PIO		AT91C_PIO_PB22
173 #endif
174 
175 /*
176  * NOR Flash
177  */
178 #define CONFIG_SYS_FLASH_BASE			0x10000000
179 #define PHYS_FLASH_SIZE				0x800000	/* 8MB */
180 #define CONFIG_SYS_FLASH_CFI			1
181 #define CONFIG_FLASH_CFI_DRIVER			1
182 #define CONFIG_SYS_MAX_FLASH_BANKS		1
183 #define CONFIG_SYS_MAX_FLASH_SECT		256
184 #define CONFIG_SYS_FLASH_PROTECTION
185 
186 /*
187  * Environment Settings
188  */
189 #ifdef CONFIG_ENV_IS_IN_DATAFLASH
190 /*
191  * Datasflash Environment Settings
192  */
193 #define CONFIG_ENV_OFFSET			0x4200
194 #define CONFIG_ENV_ADDR			\
195 		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
196 /* 8 * 1056 really , but start.s is not OK with this*/
197 #define CONFIG_ENV_SIZE			0x2000
198 
199 #else
200 /*
201  * NOR Flash Environment Settings
202  */
203 #define CONFIG_ENV_IS_IN_FLASH		1
204 
205 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
206 /*
207  * between boot.bin and u-boot.bin.gz
208  */
209 #define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + 0xe000)
210 #define CONFIG_ENV_SIZE			0x10000 /* sectors are 64K here */
211 #else
212 /*
213  * after u-boot.bin
214  */
215 #define CONFIG_ENV_ADDR			\
216 		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
217 #define CONFIG_ENV_SIZE			0x10000 /* sectors are 64K here */
218 /* The following #defines are needed to get flash environment right */
219 #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
220 #define CONFIG_SYS_MONITOR_LEN		\
221 		(CONFIG_SYS_BOOT_SIZE + CONFIG_SYS_U_BOOT_SIZE)
222 #endif	/* CONFIG_SKIP_LOWLEVEL_INIT */
223 
224 #endif	/* CONFIG_ENV_IS_IN_DATAFLASH */
225 
226 /*
227  * Boot option
228  */
229 #define CONFIG_BOOTDELAY		3
230 
231 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
232 /* boot.bin, env, u-boot.bin.gz */
233 #define CONFIG_SYS_BOOT_SIZE		0x6000 /* 24 KBytes */
234 #define CONFIG_SYS_U_BOOT_BASE		(CONFIG_SYS_FLASH_BASE + 0x10000)
235 #define CONFIG_SYS_U_BOOT_SIZE		0x10000 /* 64 KBytes */
236 #else
237 /* u-boot.bin */
238 #define CONFIG_SYS_BOOT_SIZE		0x0 /* 0 KBytes */
239 #define CONFIG_SYS_U_BOOT_BASE		CONFIG_SYS_FLASH_BASE
240 #define CONFIG_SYS_U_BOOT_SIZE		0x40000 /* 128 KBytes */
241 #endif /* CONFIG_SKIP_LOWLEVEL_INIT */
242 
243 #define CONFIG_SYS_LOAD_ADDR		0x21000000 /* default load address */
244 #define CONFIG_ENV_OVERWRITE	1
245 
246 /*
247  * USB Config
248  */
249 #define CONFIG_CMD_USB
250 #define CONFIG_USB_OHCI_NEW	1
251 #define CONFIG_USB_KEYBOARD	1
252 #define CONFIG_USB_STORAGE	1
253 #define CONFIG_DOS_PARTITION	1
254 
255 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
256 #define CONFIG_SYS_USB_OHCI_CPU_INIT		1
257 #define CONFIG_SYS_USB_OHCI_REGS_BASE		AT91_USB_HOST_BASE
258 #define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91rm9200"
259 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
260 
261 /*
262  * I2C
263  */
264 #define CONFIG_HARD_I2C
265 
266 #ifdef CONFIG_HARD_I2C
267 #define CONFIG_CMD_I2C
268 #define CONFIG_I2C_CMD_TREE
269 #define CONFIG_SYS_I2C_SPEED		0	/* not used */
270 #define CONFIG_SYS_I2C_SLAVE		0	/* not used */
271 #endif
272 
273 /*
274  * Shell Settings
275  */
276 #define CONFIG_CMDLINE_EDITING		1
277 #define CONFIG_SYS_LONGHELP		1
278 #define CONFIG_AUTO_COMPLETE		1
279 #define CONFIG_SYS_HUSH_PARSER		1
280 #define CONFIG_SYS_PROMPT		"U-Boot> "
281 #define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
282 #define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
283 #define CONFIG_SYS_MAXARGS		16	/* max number of command args */
284 /* Print Buffer Size */
285 #define CONFIG_SYS_PBSIZE		\
286 		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
287 
288 #ifndef __ASSEMBLY__
289 /*-----------------------------------------------------------------------
290  * Board specific extension for bd_info
291  *
292  * This structure is embedded in the global bd_info (bd_t) structure
293  * and can be used by the board specific code (eg board/...)
294  */
295 
296 struct bd_info_ext {
297 	/* helper variable for board environment handling
298 	 *
299 	 * env_crc_valid == 0	=>	uninitialised
300 	 * env_crc_valid > 0	=>	environment crc in flash is valid
301 	 * env_crc_valid < 0	=>	environment crc in flash is invalid
302 	 */
303 	int env_crc_valid;
304 };
305 #endif
306 
307 #define CONFIG_SYS_HZ 1000
308 /*
309  * AT91C_TC0_CMR is implicitly set to
310  * AT91C_TC_TIMER_DIV1_CLOCK
311  */
312 #define CONFIG_SYS_HZ_CLOCK (AT91C_MASTER_CLOCK / 2)
313 
314 #define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
315 /*
316  * Size of malloc() pool
317  */
318 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024 \
319 					     , 0x1000)
320 /* size in bytes reserved for initial data */
321 #define CONFIG_SYS_GBL_DATA_SIZE	128
322 
323 #define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
324 #define CONFIG_STACKSIZE_IRQ		(4 * 1024) /* Unsure if to big or to small*/
325 #define CONFIG_STACKSIZE_FIQ		(4 * 1024) /* Unsure if to big or to small*/
326 #endif
327