xref: /rk3399_rockchip-uboot/include/configs/arndale.h (revision 2be296538e2e9d2893dc495b3fc8f9f6acb1454c)
1a2ac68fbSChander Kashyap /*
2a2ac68fbSChander Kashyap  * Copyright (C) 2013 Samsung Electronics
3a2ac68fbSChander Kashyap  *
4a2ac68fbSChander Kashyap  * SPDX-License-Identifier:	GPL-2.0+
5a2ac68fbSChander Kashyap  *
6a2ac68fbSChander Kashyap  * Configuration settings for the SAMSUNG Arndale board.
7a2ac68fbSChander Kashyap  */
8a2ac68fbSChander Kashyap 
9a2ac68fbSChander Kashyap #ifndef __CONFIG_ARNDALE_H
10a2ac68fbSChander Kashyap #define __CONFIG_ARNDALE_H
11a2ac68fbSChander Kashyap 
12e6825e03SIan Campbell #define EXYNOS_FDTFILE_SETTING \
13e6825e03SIan Campbell 	"fdtfile=exynos5250-arndale.dtb\0"
14e6825e03SIan Campbell 
15f94de733SSimon Glass #include "exynos5250-common.h"
16*bf637ea5SSimon Glass #include <configs/exynos5-common.h>
17a2ac68fbSChander Kashyap 
18a2ac68fbSChander Kashyap /* SD/MMC configuration */
19a2ac68fbSChander Kashyap #define CONFIG_SUPPORT_EMMC_BOOT
20a2ac68fbSChander Kashyap 
21a2ac68fbSChander Kashyap /* allow to overwrite serial and ethaddr */
22a2ac68fbSChander Kashyap #define CONFIG_ENV_OVERWRITE
23a2ac68fbSChander Kashyap 
24a2ac68fbSChander Kashyap /* MMC SPL */
25e106bd9bSRajeshwari Birje #define CONFIG_EXYNOS_SPL
26a2ac68fbSChander Kashyap 
27a2ac68fbSChander Kashyap /* Miscellaneous configurable options */
28a2ac68fbSChander Kashyap #define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
29a2ac68fbSChander Kashyap 
30a2ac68fbSChander Kashyap #define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
31a2ac68fbSChander Kashyap 
32a2ac68fbSChander Kashyap #define CONFIG_IRAM_STACK	0x02050000
33a2ac68fbSChander Kashyap 
34a2ac68fbSChander Kashyap #define CONFIG_SYS_INIT_SP_ADDR	CONFIG_IRAM_STACK
35a2ac68fbSChander Kashyap 
36a2ac68fbSChander Kashyap /* PMIC */
37*bf637ea5SSimon Glass #define CONFIG_POWER
38913702caSSimon Glass #define CONFIG_POWER_I2C
39a2ac68fbSChander Kashyap 
40f8caed31STushar Behera #define CONFIG_PREBOOT
41f8caed31STushar Behera 
42fafbc6c0SAndre Przywara #define CONFIG_S5P_PA_SYSRAM	0x02020000
43fafbc6c0SAndre Przywara #define CONFIG_SMP_PEN_ADDR	CONFIG_S5P_PA_SYSRAM
44fafbc6c0SAndre Przywara 
45fafbc6c0SAndre Przywara /* The PERIPHBASE in the CBAR register is wrong on the Arndale, so override it */
46fafbc6c0SAndre Przywara #define CONFIG_ARM_GIC_BASE_ADDRESS	0x10480000
47fafbc6c0SAndre Przywara 
48d4061aa0SSimon Glass /* Power */
49d4061aa0SSimon Glass #define CONFIG_POWER
50d4061aa0SSimon Glass #define CONFIG_POWER_I2C
51d4061aa0SSimon Glass 
52a2ac68fbSChander Kashyap #endif	/* __CONFIG_H */
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