1 /* 2 * (C) Copyright 2015 3 * (C) Copyright 2014 4 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 5 * 6 * Based on: 7 * Copyright (C) 2012 Freescale Semiconductor, Inc. 8 * 9 * Configuration settings for the Freescale i.MX6Q SabreSD board. 10 * 11 * SPDX-License-Identifier: GPL-2.0+ 12 */ 13 #ifndef __ARISTAINETOS_COMMON_CONFIG_H 14 #define __ARISTAINETOS_COMMON_CONFIG_H 15 16 #include "mx6_common.h" 17 18 #define CONFIG_MACH_TYPE 4501 19 #define CONFIG_MMCROOT "/dev/mmcblk0p1" 20 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) 21 22 /* Size of malloc() pool */ 23 #define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) 24 25 #define CONFIG_BOARD_EARLY_INIT_F 26 27 #define CONFIG_MXC_UART 28 29 #define CONFIG_CMD_FUSE 30 #define CONFIG_MXC_OCOTP 31 32 /* MMC Configs */ 33 #define CONFIG_FSL_ESDHC 34 #define CONFIG_FSL_USDHC 35 #define CONFIG_SYS_FSL_ESDHC_ADDR 0 36 37 #define CONFIG_MMC 38 #define CONFIG_CMD_MMC 39 #define CONFIG_GENERIC_MMC 40 #define CONFIG_BOUNCE_BUFFER 41 42 #define CONFIG_CMD_PING 43 #define CONFIG_CMD_DHCP 44 #define CONFIG_CMD_MII 45 #define CONFIG_CMD_NET 46 #define CONFIG_FEC_MXC 47 #define CONFIG_MII 48 #define IMX_FEC_BASE ENET_BASE_ADDR 49 #define CONFIG_ETHPRIME "FEC" 50 #define CONFIG_FEC_MXC_PHYADDR 0 51 52 #define CONFIG_PHYLIB 53 #define CONFIG_PHY_MICREL 54 55 #define CONFIG_CMD_SF 56 #define CONFIG_SPI_FLASH 57 #define CONFIG_SPI_FLASH_MTD 58 #define CONFIG_SPI_FLASH_STMICRO 59 #define CONFIG_MXC_SPI 60 #define CONFIG_SF_DEFAULT_BUS 3 61 #define CONFIG_SF_DEFAULT_SPEED 20000000 62 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 63 #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN 64 65 /* Command definition */ 66 #define CONFIG_CMD_BMODE 67 #define CONFIG_CMD_SETEXPR 68 69 #define CONFIG_EXTRA_ENV_SETTINGS \ 70 "script=u-boot.scr\0" \ 71 "fit_file=/boot/system.itb\0" \ 72 "loadaddr=0x12000000\0" \ 73 "fit_addr_r=0x14000000\0" \ 74 "uboot=/boot/u-boot.imx\0" \ 75 "uboot_sz=d0000\0" \ 76 "rescue_sys_addr=f0000\0" \ 77 "rescue_sys_length=f10000\0" \ 78 "panel=lb07wv8\0" \ 79 "splashpos=m,m\0" \ 80 "console=" CONFIG_CONSOLE_DEV "\0" \ 81 "fdt_high=0xffffffff\0" \ 82 "initrd_high=0xffffffff\0" \ 83 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 84 "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ 85 "default ${board_type}\0" \ 86 "get_env=mw ${loadaddr} 0 0x20000;" \ 87 "mmc rescan;" \ 88 "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ 89 "env import -t ${loadaddr}\0" \ 90 "default_env=mw ${loadaddr} 0 0x20000;" \ 91 "env export -t ${loadaddr} serial# ethaddr eth1addr " \ 92 "board_type panel;" \ 93 "env default -a;" \ 94 "env import -t ${loadaddr}\0" \ 95 "loadbootscript=" \ 96 "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ 97 "bootscript=echo Running bootscript from mmc ...; " \ 98 "source\0" \ 99 "mmcpart=1\0" \ 100 "mmcdev=0\0" \ 101 "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ 102 "mmcargs=setenv bootargs console=${console},${baudrate} " \ 103 "root=${mmcroot}\0" \ 104 "mmcboot=echo Booting from mmc ...; " \ 105 "run mmcargs addmtd addmisc set_fit_default;" \ 106 "bootm ${fit_addr_r}\0" \ 107 "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ 108 "${fit_file}\0" \ 109 "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ 110 "${uboot}\0" \ 111 "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ 112 "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ 113 "setexpr uboot_maxsize ${uboot_sz} - 400;" \ 114 "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ 115 "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ 116 "sf write ${loadaddr} 400 ${filesize};" \ 117 "sf read ${cmp_buf} 400 ${uboot_sz};" \ 118 "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ 119 "ubiboot=echo Booting from ubi ...; " \ 120 "run ubiargs addmtd addmisc set_fit_default;" \ 121 "bootm ${fit_addr_r}\0" \ 122 "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \ 123 "ubifsload ${fit_addr_r} /boot/system.itb; " \ 124 "imi ${fit_addr_r}\0 " \ 125 "rescueargs=setenv bootargs console=${console},${baudrate} " \ 126 "root=/dev/ram rw\0 " \ 127 "rescueboot=echo Booting rescue system from NOR ...; " \ 128 "run rescueargs addmtd addmisc set_fit_default;" \ 129 "bootm ${fit_addr_r}\0" \ 130 "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ 131 "${rescue_sys_length}; imi ${fit_addr_r}\0" \ 132 CONFIG_EXTRA_ENV_BOARD_SETTINGS 133 134 #define CONFIG_BOOTCOMMAND \ 135 "mmc dev ${mmcdev};" \ 136 "if mmc rescan; then " \ 137 "if run loadbootscript; then " \ 138 "run bootscript; " \ 139 "else " \ 140 "if run mmc_load_fit; then " \ 141 "run mmcboot; " \ 142 "else " \ 143 "if run ubifs_load_fit; then " \ 144 "run ubiboot; " \ 145 "else " \ 146 "if run rescue_load_fit; then " \ 147 "run rescueboot; " \ 148 "else " \ 149 "echo RESCUE SYSTEM BOOT " \ 150 "FAILURE;" \ 151 "fi; " \ 152 "fi; " \ 153 "fi; " \ 154 "fi; " \ 155 "else " \ 156 "if run ubifs_load_fit; then " \ 157 "run ubiboot; " \ 158 "else " \ 159 "if run rescue_load_fit; then " \ 160 "run rescueboot; " \ 161 "else " \ 162 "echo RESCUE SYSTEM BOOT FAILURE;" \ 163 "fi; " \ 164 "fi; " \ 165 "fi" 166 167 #define CONFIG_ARP_TIMEOUT 200UL 168 169 /* Print Buffer Size */ 170 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 171 172 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM 173 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) 174 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 175 176 #define CONFIG_STACKSIZE (128 * 1024) 177 178 /* Physical Memory Map */ 179 #define CONFIG_NR_DRAM_BANKS 1 180 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR 181 182 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM 183 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR 184 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE 185 186 #define CONFIG_SYS_INIT_SP_OFFSET \ 187 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 188 #define CONFIG_SYS_INIT_SP_ADDR \ 189 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) 190 191 /* Environment organization */ 192 #define CONFIG_ENV_SIZE (12 * 1024) 193 #define CONFIG_ENV_IS_IN_SPI_FLASH 194 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 195 #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS 196 #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS 197 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 198 #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE 199 #define CONFIG_ENV_SECT_SIZE (0x010000) 200 #define CONFIG_ENV_OFFSET (0x0d0000) 201 #define CONFIG_ENV_OFFSET_REDUND (0x0e0000) 202 203 #define CONFIG_CMD_CACHE 204 205 #define CONFIG_SYS_FSL_USDHC_NUM 2 206 207 /* I2C */ 208 #define CONFIG_CMD_I2C 209 #define CONFIG_SYS_I2C 210 #define CONFIG_SYS_I2C_MXC 211 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ 212 #define CONFIG_SYS_I2C_SPEED 100000 213 #define CONFIG_SYS_I2C_SLAVE 0x7f 214 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } 215 216 /* NAND stuff */ 217 #define CONFIG_CMD_NAND 218 #define CONFIG_CMD_NAND_TRIMFFS 219 #define CONFIG_NAND_MXS 220 #define CONFIG_SYS_MAX_NAND_DEVICE 1 221 #define CONFIG_SYS_NAND_BASE 0x40000000 222 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 223 #define CONFIG_SYS_NAND_ONFI_DETECTION 224 225 /* DMA stuff, needed for GPMI/MXS NAND support */ 226 #define CONFIG_APBH_DMA 227 #define CONFIG_APBH_DMA_BURST 228 #define CONFIG_APBH_DMA_BURST8 229 230 /* RTC */ 231 #define CONFIG_SYS_I2C_RTC_ADDR 0x68 232 #define CONFIG_SYS_RTC_BUS_NUM 2 233 #define CONFIG_RTC_M41T11 234 #define CONFIG_CMD_DATE 235 236 /* USB Configs */ 237 #define CONFIG_CMD_USB 238 #define CONFIG_USB_EHCI 239 #define CONFIG_USB_EHCI_MX6 240 #define CONFIG_USB_STORAGE 241 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 242 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ 243 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) 244 #define CONFIG_MXC_USB_FLAGS 0 245 246 /* UBI support */ 247 #define CONFIG_LZO 248 #define CONFIG_CMD_MTDPARTS 249 #define CONFIG_MTD_PARTITIONS 250 #define CONFIG_MTD_DEVICE 251 #define CONFIG_RBTREE 252 #define CONFIG_CMD_UBI 253 #define CONFIG_CMD_UBIFS 254 255 #define CONFIG_MTD_UBI_FASTMAP 256 #define CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT 1 257 258 #define CONFIG_HW_WATCHDOG 259 #define CONFIG_IMX_WATCHDOG 260 261 #define CONFIG_FIT 262 263 /* Framebuffer */ 264 #define CONFIG_VIDEO 265 #define CONFIG_VIDEO_IPUV3 266 /* check this console not needed, after test remove it */ 267 #define CONFIG_CFB_CONSOLE 268 #define CONFIG_VGA_AS_SINGLE_DEVICE 269 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 270 #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 271 #define CONFIG_VIDEO_BMP_RLE8 272 #define CONFIG_SPLASH_SCREEN 273 #define CONFIG_SPLASH_SCREEN_ALIGN 274 #define CONFIG_BMP_16BPP 275 #define CONFIG_VIDEO_LOGO 276 #define CONFIG_VIDEO_BMP_LOGO 277 #define CONFIG_IPUV3_CLK 198000000 278 #define CONFIG_IMX_VIDEO_SKIP 279 280 #define CONFIG_CMD_BMP 281 282 #define CONFIG_PWM_IMX 283 #define CONFIG_IMX6_PWM_PER_CLK 66000000 284 285 #endif /* __ARISTAINETOS_COMMON_CONFIG_H */ 286