1 /* 2 * 3 * Configuration settings for the Armadeus Project motherboard APF27 4 * 5 * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #ifndef __CONFIG_H 11 #define __CONFIG_H 12 13 #define CONFIG_ENV_VERSION 10 14 #define CONFIG_IDENT_STRING " apf27 patch 3.10" 15 #define CONFIG_BOARD_NAME apf27 16 17 /* 18 * SoC configurations 19 */ 20 #define CONFIG_MX27 /* This is a Freescale i.MX27 Chip */ 21 #define CONFIG_MACH_TYPE 1698 /* APF27 */ 22 23 /* 24 * Enable the call to miscellaneous platform dependent initialization. 25 */ 26 #define CONFIG_SYS_NO_FLASH 27 28 /* 29 * Board display option 30 */ 31 #define CONFIG_DISPLAY_BOARDINFO 32 #define CONFIG_DISPLAY_CPUINFO 33 34 /* 35 * SPL 36 */ 37 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" 38 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" 39 #define CONFIG_SPL_MAX_SIZE 2048 40 #define CONFIG_SPL_TEXT_BASE 0xA0000000 41 #define CONFIG_SPL_SERIAL_SUPPORT 42 43 /* NAND boot config */ 44 #define CONFIG_SPL_NAND_SUPPORT 45 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 46 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 47 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE 48 #define CONFIG_SYS_NAND_U_BOOT_SIZE CONFIG_SYS_MONITOR_LEN - 0x800 49 50 /* 51 * BOOTP options 52 */ 53 #define CONFIG_BOOTP_SUBNETMASK 54 #define CONFIG_BOOTP_GATEWAY 55 #define CONFIG_BOOTP_HOSTNAME 56 #define CONFIG_BOOTP_BOOTPATH 57 #define CONFIG_BOOTP_BOOTFILESIZE 58 #define CONFIG_BOOTP_DNS 59 #define CONFIG_BOOTP_DNS2 60 61 #define CONFIG_HOSTNAME CONFIG_BOARD_NAME 62 #define CONFIG_ROOTPATH "/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root" 63 64 /* 65 * U-Boot Commands 66 */ 67 #define CONFIG_CMD_BSP /* Board Specific functions */ 68 #define CONFIG_CMD_DATE 69 #define CONFIG_CMD_EEPROM 70 #define CONFIG_CMD_IMX_FUSE /* imx iim fuse */ 71 #define CONFIG_CMD_MTDPARTS /* MTD partition support */ 72 #define CONFIG_CMD_NAND /* NAND support */ 73 #define CONFIG_CMD_NAND_LOCK_UNLOCK 74 #define CONFIG_CMD_NAND_TRIMFFS 75 #define CONFIG_CMD_UBI 76 #define CONFIG_CMD_UBIFS 77 78 /* 79 * Memory configurations 80 */ 81 #define CONFIG_NR_DRAM_POPULATED 1 82 #define CONFIG_NR_DRAM_BANKS 2 83 84 #define ACFG_SDRAM_MBYTE_SYZE 64 85 86 #define PHYS_SDRAM_1 0xA0000000 87 #define PHYS_SDRAM_2 0xB0000000 88 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 89 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (512<<10)) 90 #define CONFIG_SYS_MEMTEST_START 0xA0000000 /* memtest test area */ 91 #define CONFIG_SYS_MEMTEST_END 0xA0300000 /* 3 MiB RAM test */ 92 93 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE \ 94 + PHYS_SDRAM_1_SIZE - 0x0100000) 95 96 #define CONFIG_SYS_TEXT_BASE 0xA0000800 97 98 /* 99 * FLASH organization 100 */ 101 #define ACFG_MONITOR_OFFSET 0x00000000 102 #define CONFIG_SYS_MONITOR_LEN 0x00100000 /* 1MiB */ 103 #define CONFIG_ENV_IS_IN_NAND 104 #define CONFIG_ENV_OVERWRITE 105 #define CONFIG_ENV_OFFSET 0x00100000 /* NAND offset */ 106 #define CONFIG_ENV_SIZE 0x00020000 /* 128kB */ 107 #define CONFIG_ENV_RANGE 0X00080000 /* 512kB */ 108 #define CONFIG_ENV_OFFSET_REDUND \ 109 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) /* +512kB */ 110 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE /* 512kB */ 111 #define CONFIG_FIRMWARE_OFFSET 0x00200000 112 #define CONFIG_FIRMWARE_SIZE 0x00080000 /* 512kB */ 113 #define CONFIG_KERNEL_OFFSET 0x00300000 114 #define CONFIG_ROOTFS_OFFSET 0x00800000 115 116 #define CONFIG_MTDMAP "mxc_nand.0" 117 #define MTDIDS_DEFAULT "nand0=" CONFIG_MTDMAP 118 #define MTDPARTS_DEFAULT "mtdparts=" CONFIG_MTDMAP \ 119 ":1M(u-boot)ro," \ 120 "512K(env)," \ 121 "512K(env2)," \ 122 "512K(firmware)," \ 123 "512K(dtb)," \ 124 "5M(kernel)," \ 125 "-(rootfs)" 126 127 /* 128 * U-Boot general configurations 129 */ 130 #define CONFIG_SYS_LONGHELP 131 #define CONFIG_SYS_CBSIZE 2048 /* console I/O buffer */ 132 #define CONFIG_SYS_PBSIZE \ 133 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) 134 /* Print buffer size */ 135 #define CONFIG_SYS_MAXARGS 16 /* max command args */ 136 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 137 /* Boot argument buffer size */ 138 #define CONFIG_AUTO_COMPLETE 139 #define CONFIG_CMDLINE_EDITING 140 #define CONFIG_ENV_VARS_UBOOT_CONFIG 141 #define CONFIG_PREBOOT "run check_flash check_env;" 142 143 /* 144 * Boot Linux 145 */ 146 #define CONFIG_CMDLINE_TAG /* send commandline to Kernel */ 147 #define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */ 148 #define CONFIG_INITRD_TAG /* send initrd params */ 149 150 #define CONFIG_BOOTFILE __stringify(CONFIG_BOARD_NAME) "-linux.bin" 151 #define CONFIG_BOOTARGS "console=" __stringify(ACFG_CONSOLE_DEV) "," \ 152 __stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \ 153 " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs " 154 155 #define ACFG_CONSOLE_DEV ttySMX0 156 #define CONFIG_BOOTCOMMAND "run ubifsboot" 157 #define CONFIG_SYS_AUTOLOAD "no" 158 /* 159 * Default load address for user programs and kernel 160 */ 161 #define CONFIG_LOADADDR 0xA0000000 162 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR 163 164 /* 165 * Extra Environments 166 */ 167 #define CONFIG_EXTRA_ENV_SETTINGS \ 168 "env_version=" __stringify(CONFIG_ENV_VERSION) "\0" \ 169 "consoledev=" __stringify(ACFG_CONSOLE_DEV) "\0" \ 170 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 171 "partition=nand0,6\0" \ 172 "u-boot_addr=" __stringify(ACFG_MONITOR_OFFSET) "\0" \ 173 "env_addr=" __stringify(CONFIG_ENV_OFFSET) "\0" \ 174 "firmware_addr=" __stringify(CONFIG_FIRMWARE_OFFSET) "\0" \ 175 "firmware_size=" __stringify(CONFIG_FIRMWARE_SIZE) "\0" \ 176 "kernel_addr=" __stringify(CONFIG_KERNEL_OFFSET) "\0" \ 177 "rootfs_addr=" __stringify(CONFIG_ROOTFS_OFFSET) "\0" \ 178 "board_name=" __stringify(CONFIG_BOARD_NAME) "\0" \ 179 "kernel_addr_r=A0000000\0" \ 180 "check_env=if test -n ${flash_env_version}; " \ 181 "then env default env_version; " \ 182 "else env set flash_env_version ${env_version}; env save; "\ 183 "fi; " \ 184 "if itest ${flash_env_version} < ${env_version}; then " \ 185 "echo \"*** Warning - Environment version" \ 186 " change suggests: run flash_reset_env; reset\"; "\ 187 "env default flash_reset_env; "\ 188 "fi; \0" \ 189 "check_flash=nand lock; nand unlock ${env_addr}; \0" \ 190 "flash_reset_env=env default -f -a; saveenv; run update_env;" \ 191 "echo Flash environment variables erased!\0" \ 192 "download_uboot=tftpboot ${loadaddr} ${board_name}" \ 193 "-u-boot-with-spl.bin\0" \ 194 "flash_uboot=nand unlock ${u-boot_addr} ;" \ 195 "nand erase.part u-boot;" \ 196 "if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\ 197 "then nand lock; nand unlock ${env_addr};" \ 198 "echo Flashing of uboot succeed;" \ 199 "else echo Flashing of uboot failed;" \ 200 "fi; \0" \ 201 "update_uboot=run download_uboot flash_uboot\0" \ 202 "download_env=tftpboot ${loadaddr} ${board_name}" \ 203 "-u-boot-env.txt\0" \ 204 "flash_env=env import -t ${loadaddr}; env save; \0" \ 205 "update_env=run download_env flash_env\0" \ 206 "update_all=run update_env update_uboot\0" \ 207 "unlock_regs=mw 10000008 0; mw 10020008 0\0" \ 208 209 /* 210 * Serial Driver 211 */ 212 #define CONFIG_MXC_UART 213 #define CONFIG_CONS_INDEX 1 214 #define CONFIG_BAUDRATE 115200 215 #define CONFIG_MXC_UART_BASE UART1_BASE 216 217 /* 218 * GPIO 219 */ 220 #define CONFIG_MXC_GPIO 221 222 /* 223 * NOR 224 */ 225 226 /* 227 * NAND 228 */ 229 #define CONFIG_NAND_MXC 230 231 #define CONFIG_MXC_NAND_REGS_BASE 0xD8000000 232 #define CONFIG_SYS_NAND_BASE CONFIG_MXC_NAND_REGS_BASE 233 #define CONFIG_SYS_MAX_NAND_DEVICE 1 234 235 #define CONFIG_MXC_NAND_HWECC 236 #define CONFIG_SYS_NAND_LARGEPAGE 237 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 238 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 239 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 240 #define CONFIG_SYS_NAND_PAGE_COUNT CONFIG_SYS_NAND_BLOCK_SIZE / \ 241 CONFIG_SYS_NAND_PAGE_SIZE 242 #define CONFIG_SYS_NAND_SIZE (256 * 1024 * 1024) 243 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 11 244 #define NAND_MAX_CHIPS 1 245 246 #define CONFIG_FLASH_SHOW_PROGRESS 45 247 #define CONFIG_SYS_NAND_QUIET 1 248 249 /* 250 * Partitions & Filsystems 251 */ 252 #define CONFIG_MTD_DEVICE 253 #define CONFIG_MTD_PARTITIONS 254 #define CONFIG_DOS_PARTITION 255 #define CONFIG_SUPPORT_VFAT 256 257 /* 258 * UBIFS 259 */ 260 #define CONFIG_RBTREE 261 #define CONFIG_LZO 262 263 /* 264 * Ethernet (on SOC imx FEC) 265 */ 266 #define CONFIG_FEC_MXC 267 #define CONFIG_FEC_MXC_PHYADDR 0x1f 268 #define CONFIG_MII /* MII PHY management */ 269 270 /* 271 * FPGA 272 */ 273 #ifndef CONFIG_SPL_BUILD 274 #define CONFIG_FPGA 275 #endif 276 #define CONFIG_FPGA_COUNT 1 277 #define CONFIG_FPGA_XILINX 278 #define CONFIG_FPGA_SPARTAN3 279 #define CONFIG_SYS_FPGA_WAIT 250 /* 250 ms */ 280 #define CONFIG_SYS_FPGA_PROG_FEEDBACK 281 #define CONFIG_SYS_FPGA_CHECK_CTRLC 282 #define CONFIG_SYS_FPGA_CHECK_ERROR 283 284 /* 285 * Fuses - IIM 286 */ 287 #ifdef CONFIG_CMD_IMX_FUSE 288 #define IIM_MAC_BANK 0 289 #define IIM_MAC_ROW 5 290 #define IIM0_SCC_KEY 11 291 #define IIM1_SUID 1 292 #endif 293 294 /* 295 * I2C 296 */ 297 298 #ifdef CONFIG_CMD_I2C 299 #define CONFIG_SYS_I2C 300 #define CONFIG_SYS_I2C_MXC 301 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ 302 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ 303 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 /* 100 kHz */ 304 #define CONFIG_SYS_MXC_I2C1_SLAVE 0x7F 305 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 /* 100 kHz */ 306 #define CONFIG_SYS_MXC_I2C2_SLAVE 0x7F 307 #define CONFIG_SYS_I2C_NOPROBES { } 308 309 #ifdef CONFIG_CMD_EEPROM 310 # define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM 24LC02 */ 311 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ 312 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 313 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* msec */ 314 #endif /* CONFIG_CMD_EEPROM */ 315 #endif /* CONFIG_CMD_I2C */ 316 317 /* 318 * SD/MMC 319 */ 320 #ifdef CONFIG_CMD_MMC 321 #define CONFIG_MMC 322 #define CONFIG_GENERIC_MMC 323 #define CONFIG_MXC_MMC 324 #define CONFIG_MXC_MCI_REGS_BASE 0x10014000 325 #endif 326 327 /* 328 * RTC 329 */ 330 #ifdef CONFIG_CMD_DATE 331 #define CONFIG_RTC_DS1374 332 #define CONFIG_SYS_RTC_BUS_NUM 0 333 #endif /* CONFIG_CMD_DATE */ 334 335 /* 336 * PLL 337 * 338 * 31 | x |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0 339 * |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------| 340 */ 341 #define CONFIG_MX27_CLK32 32768 /* 32768 or 32000 Hz crystal */ 342 343 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */ 344 /* micron 64MB */ 345 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 346 #define PHYS_SDRAM_2_SIZE 0x04000000 /* 64 MB */ 347 #endif 348 349 #if (ACFG_SDRAM_MBYTE_SYZE == 128) 350 /* micron 128MB */ 351 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 352 #define PHYS_SDRAM_2_SIZE 0x08000000 /* 128 MB */ 353 #endif 354 355 #if (ACFG_SDRAM_MBYTE_SYZE == 256) 356 /* micron 256MB */ 357 #define PHYS_SDRAM_1_SIZE 0x10000000 /* 256 MB */ 358 #define PHYS_SDRAM_2_SIZE 0x10000000 /* 256 MB */ 359 #endif 360 361 #endif /* __CONFIG_H */ 362