xref: /rk3399_rockchip-uboot/include/configs/apf27.h (revision 3f8f1410b5d5d1fcbc28ea06700a9b601d736575)
1 /*
2  *
3  * Configuration settings for the Armadeus Project motherboard APF27
4  *
5  * Copyright (C) 2008-2013 Eric Jarrige <eric.jarrige@armadeus.org>
6  *
7  * SPDX-License-Identifier:    GPL-2.0+
8  */
9 
10 #ifndef __CONFIG_H
11 #define __CONFIG_H
12 
13 #define CONFIG_ENV_VERSION	10
14 #define CONFIG_BOARD_NAME apf27
15 
16 /*
17  * SoC configurations
18  */
19 #define CONFIG_MX27			/* This is a Freescale i.MX27 Chip */
20 #define CONFIG_MACH_TYPE	1698	/* APF27 */
21 
22 /*
23  * Enable the call to miscellaneous platform dependent initialization.
24  */
25 
26 /*
27  * SPL
28  */
29 #define CONFIG_SPL_TARGET	"u-boot-with-spl.bin"
30 #define CONFIG_SPL_MAX_SIZE	2048
31 #define CONFIG_SPL_TEXT_BASE    0xA0000000
32 
33 /* NAND boot config */
34 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_TEXT_BASE
35 #define CONFIG_SYS_NAND_U_BOOT_OFFS	0x800
36 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
37 #define CONFIG_SYS_NAND_U_BOOT_SIZE	CONFIG_SYS_MONITOR_LEN - 0x800
38 
39 /*
40  * BOOTP options
41  */
42 #define CONFIG_BOOTP_SUBNETMASK
43 #define CONFIG_BOOTP_GATEWAY
44 #define CONFIG_BOOTP_HOSTNAME
45 #define CONFIG_BOOTP_BOOTPATH
46 #define CONFIG_BOOTP_BOOTFILESIZE
47 #define CONFIG_BOOTP_DNS
48 #define CONFIG_BOOTP_DNS2
49 
50 #define CONFIG_HOSTNAME	CONFIG_BOARD_NAME
51 #define CONFIG_ROOTPATH	"/tftpboot/" __stringify(CONFIG_BOARD_NAME) "-root"
52 
53 /*
54  * Memory configurations
55  */
56 #define CONFIG_NR_DRAM_POPULATED 1
57 #define CONFIG_NR_DRAM_BANKS	2
58 
59 #define ACFG_SDRAM_MBYTE_SYZE 64
60 
61 #define PHYS_SDRAM_1			0xA0000000
62 #define PHYS_SDRAM_2			0xB0000000
63 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
64 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (512<<10))
65 #define CONFIG_SYS_MEMTEST_START	0xA0000000	/* memtest test area  */
66 #define CONFIG_SYS_MEMTEST_END		0xA0300000	/* 3 MiB RAM test */
67 
68 #define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE	\
69 		+ PHYS_SDRAM_1_SIZE - 0x0100000)
70 
71 #define CONFIG_SYS_TEXT_BASE		0xA0000800
72 
73 /*
74  * FLASH organization
75  */
76 #define	ACFG_MONITOR_OFFSET		0x00000000
77 #define	CONFIG_SYS_MONITOR_LEN		0x00100000	/* 1MiB */
78 #define	CONFIG_ENV_OVERWRITE
79 #define	CONFIG_ENV_OFFSET		0x00100000	/* NAND offset */
80 #define	CONFIG_ENV_SIZE			0x00020000	/* 128kB  */
81 #define CONFIG_ENV_RANGE		0X00080000	/* 512kB */
82 #define	CONFIG_ENV_OFFSET_REDUND	\
83 		(CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)	/* +512kB */
84 #define	CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SIZE	/* 512kB */
85 #define	CONFIG_FIRMWARE_OFFSET		0x00200000
86 #define	CONFIG_FIRMWARE_SIZE		0x00080000	/* 512kB  */
87 #define	CONFIG_KERNEL_OFFSET		0x00300000
88 #define	CONFIG_ROOTFS_OFFSET		0x00800000
89 
90 #define CONFIG_MTDMAP			"mxc_nand.0"
91 #define MTDIDS_DEFAULT			"nand0=" CONFIG_MTDMAP
92 #define MTDPARTS_DEFAULT	"mtdparts=" CONFIG_MTDMAP \
93 				":1M(u-boot)ro," \
94 				"512K(env)," \
95 				"512K(env2)," \
96 				"512K(firmware)," \
97 				"512K(dtb)," \
98 				"5M(kernel)," \
99 				"-(rootfs)"
100 
101 /*
102  * U-Boot general configurations
103  */
104 #define CONFIG_SYS_LONGHELP
105 #define CONFIG_SYS_CBSIZE		2048		/* console I/O buffer */
106 #define CONFIG_SYS_PBSIZE		\
107 				(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
108 						/* Print buffer size */
109 #define CONFIG_SYS_MAXARGS		16		/* max command args */
110 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
111 						/* Boot argument buffer size */
112 #define CONFIG_AUTO_COMPLETE
113 #define CONFIG_CMDLINE_EDITING
114 #define CONFIG_ENV_VARS_UBOOT_CONFIG
115 #define CONFIG_PREBOOT			"run check_flash check_env;"
116 
117 /*
118  * Boot Linux
119  */
120 #define CONFIG_CMDLINE_TAG		/* send commandline to Kernel	*/
121 #define CONFIG_SETUP_MEMORY_TAGS	/* send memory definition to kernel */
122 #define CONFIG_INITRD_TAG		/* send initrd params	*/
123 
124 #define	CONFIG_BOOTFILE		__stringify(CONFIG_BOARD_NAME) "-linux.bin"
125 #define CONFIG_BOOTARGS		"console=" __stringify(ACFG_CONSOLE_DEV) "," \
126 			__stringify(CONFIG_BAUDRATE) " " MTDPARTS_DEFAULT \
127 			" ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs "
128 
129 #define ACFG_CONSOLE_DEV	ttySMX0
130 #define CONFIG_BOOTCOMMAND	"run ubifsboot"
131 #define CONFIG_SYS_AUTOLOAD	"no"
132 /*
133  * Default load address for user programs and kernel
134  */
135 #define CONFIG_LOADADDR			0xA0000000
136 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_LOADADDR
137 
138 /*
139  * Extra Environments
140  */
141 #define CONFIG_EXTRA_ENV_SETTINGS \
142 	"env_version="		__stringify(CONFIG_ENV_VERSION)		"\0" \
143 	"consoledev="		__stringify(ACFG_CONSOLE_DEV)		"\0" \
144 	"mtdparts="		MTDPARTS_DEFAULT			"\0" \
145 	"partition=nand0,6\0"						\
146 	"u-boot_addr="		__stringify(ACFG_MONITOR_OFFSET)	"\0" \
147 	"env_addr="		__stringify(CONFIG_ENV_OFFSET)		"\0" \
148 	"firmware_addr="	__stringify(CONFIG_FIRMWARE_OFFSET)	"\0" \
149 	"firmware_size="	__stringify(CONFIG_FIRMWARE_SIZE)	"\0" \
150 	"kernel_addr="		__stringify(CONFIG_KERNEL_OFFSET)	"\0" \
151 	"rootfs_addr="		__stringify(CONFIG_ROOTFS_OFFSET)	"\0" \
152 	"board_name="		__stringify(CONFIG_BOARD_NAME)		"\0" \
153 	"kernel_addr_r=A0000000\0" \
154 	"check_env=if test -n ${flash_env_version}; "			\
155 		"then env default env_version; "			\
156 		"else env set flash_env_version ${env_version}; env save; "\
157 		"fi; "							\
158 		"if itest ${flash_env_version} < ${env_version}; then " \
159 			"echo \"*** Warning - Environment version"	\
160 			" change suggests: run flash_reset_env; reset\"; "\
161 			"env default flash_reset_env; "\
162 		"fi; \0"						\
163 	"check_flash=nand lock; nand unlock ${env_addr}; \0"	\
164 	"flash_reset_env=env default -f -a; saveenv; run update_env;"	\
165 		"echo Flash environment variables erased!\0"		\
166 	"download_uboot=tftpboot ${loadaddr} ${board_name}"		\
167 		"-u-boot-with-spl.bin\0"				\
168 	"flash_uboot=nand unlock ${u-boot_addr} ;"			\
169 		"nand erase.part u-boot;"		\
170 		"if nand write.trimffs ${fileaddr} ${u-boot_addr} ${filesize};"\
171 			"then nand lock; nand unlock ${env_addr};"	\
172 				"echo Flashing of uboot succeed;"	\
173 			"else echo Flashing of uboot failed;"		\
174 		"fi; \0"						\
175 	"update_uboot=run download_uboot flash_uboot\0"			\
176 	"download_env=tftpboot ${loadaddr} ${board_name}"		\
177 		"-u-boot-env.txt\0"				\
178 	"flash_env=env import -t ${loadaddr}; env save; \0"		\
179 	"update_env=run download_env flash_env\0"			\
180 	"update_all=run update_env update_uboot\0"			\
181 	"unlock_regs=mw 10000008 0; mw 10020008 0\0"			\
182 
183 /*
184  * Serial Driver
185  */
186 #define CONFIG_MXC_UART
187 #define CONFIG_CONS_INDEX		1
188 #define CONFIG_MXC_UART_BASE		UART1_BASE
189 
190 /*
191  * GPIO
192  */
193 #define CONFIG_MXC_GPIO
194 
195 /*
196  * NOR
197  */
198 
199 /*
200  * NAND
201  */
202 #define CONFIG_NAND_MXC
203 
204 #define CONFIG_MXC_NAND_REGS_BASE	0xD8000000
205 #define CONFIG_SYS_NAND_BASE		CONFIG_MXC_NAND_REGS_BASE
206 #define CONFIG_SYS_MAX_NAND_DEVICE	1
207 
208 #define CONFIG_MXC_NAND_HWECC
209 #define CONFIG_SYS_NAND_LARGEPAGE
210 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT
211 #define CONFIG_SYS_NAND_PAGE_SIZE	2048
212 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
213 #define CONFIG_SYS_NAND_PAGE_COUNT	CONFIG_SYS_NAND_BLOCK_SIZE / \
214 						CONFIG_SYS_NAND_PAGE_SIZE
215 #define CONFIG_SYS_NAND_SIZE		(256 * 1024 * 1024)
216 #define CONFIG_SYS_NAND_BAD_BLOCK_POS	11
217 #define NAND_MAX_CHIPS			1
218 
219 #define CONFIG_FLASH_SHOW_PROGRESS	45
220 #define CONFIG_SYS_NAND_QUIET		1
221 
222 /*
223  * Partitions & Filsystems
224  */
225 #define CONFIG_MTD_DEVICE
226 #define CONFIG_MTD_PARTITIONS
227 #define CONFIG_SUPPORT_VFAT
228 
229 /*
230  * Ethernet (on SOC imx FEC)
231  */
232 #define CONFIG_FEC_MXC
233 #define CONFIG_FEC_MXC_PHYADDR		0x1f
234 #define CONFIG_MII				/* MII PHY management	*/
235 
236 /*
237  * FPGA
238  */
239 #ifndef CONFIG_SPL_BUILD
240 #define CONFIG_FPGA
241 #endif
242 #define CONFIG_FPGA_COUNT		1
243 #define CONFIG_FPGA_XILINX
244 #define CONFIG_FPGA_SPARTAN3
245 #define CONFIG_SYS_FPGA_WAIT		250 /* 250 ms */
246 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
247 #define CONFIG_SYS_FPGA_CHECK_CTRLC
248 #define CONFIG_SYS_FPGA_CHECK_ERROR
249 
250 /*
251  * Fuses - IIM
252  */
253 #ifdef CONFIG_CMD_IMX_FUSE
254 #define IIM_MAC_BANK		0
255 #define IIM_MAC_ROW		5
256 #define IIM0_SCC_KEY		11
257 #define IIM1_SUID		1
258 #endif
259 
260 /*
261  * I2C
262  */
263 
264 #ifdef CONFIG_CMD_I2C
265 #define CONFIG_SYS_I2C
266 #define CONFIG_SYS_I2C_MXC
267 #define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
268 #define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
269 #define CONFIG_SYS_MXC_I2C1_SPEED	100000	/* 100 kHz */
270 #define CONFIG_SYS_MXC_I2C1_SLAVE	0x7F
271 #define CONFIG_SYS_MXC_I2C2_SPEED	100000	/* 100 kHz */
272 #define CONFIG_SYS_MXC_I2C2_SLAVE	0x7F
273 #define CONFIG_SYS_I2C_NOPROBES		{ }
274 
275 #ifdef CONFIG_CMD_EEPROM
276 # define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* EEPROM 24LC02 */
277 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1	/* bytes of address */
278 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
279 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10	/* msec */
280 #endif /* CONFIG_CMD_EEPROM */
281 #endif /* CONFIG_CMD_I2C */
282 
283 /*
284  * SD/MMC
285  */
286 #ifdef CONFIG_CMD_MMC
287 #define CONFIG_MXC_MCI_REGS_BASE	0x10014000
288 #endif
289 
290 /*
291  * RTC
292  */
293 #ifdef CONFIG_CMD_DATE
294 #define CONFIG_RTC_DS1374
295 #define CONFIG_SYS_RTC_BUS_NUM		0
296 #endif /* CONFIG_CMD_DATE */
297 
298 /*
299  * PLL
300  *
301  *  31 | x  |x| x x x x |x x x x x x x x x x |x x|x x x x|x x x x x x x x x x| 0
302  *     |CPLM|X|----PD---|--------MFD---------|XXX|--MFI--|-----MFN-----------|
303  */
304 #define CONFIG_MX27_CLK32		32768	/* 32768 or 32000 Hz crystal */
305 
306 #if (ACFG_SDRAM_MBYTE_SYZE == 64) /* micron MT46H16M32LF -6 */
307 /* micron 64MB */
308 #define PHYS_SDRAM_1_SIZE			0x04000000 /* 64 MB */
309 #define PHYS_SDRAM_2_SIZE			0x04000000 /* 64 MB */
310 #endif
311 
312 #if (ACFG_SDRAM_MBYTE_SYZE == 128)
313 /* micron 128MB */
314 #define PHYS_SDRAM_1_SIZE			0x08000000 /* 128 MB */
315 #define PHYS_SDRAM_2_SIZE			0x08000000 /* 128 MB */
316 #endif
317 
318 #if (ACFG_SDRAM_MBYTE_SYZE == 256)
319 /* micron 256MB */
320 #define PHYS_SDRAM_1_SIZE			0x10000000 /* 256 MB */
321 #define PHYS_SDRAM_2_SIZE			0x10000000 /* 256 MB */
322 #endif
323 
324 #endif /* __CONFIG_H */
325