1ed01e45cSVaibhav Hiremath /* 2ed01e45cSVaibhav Hiremath * am3517_evm.h - Default configuration for AM3517 EVM board. 3ed01e45cSVaibhav Hiremath * 4ed01e45cSVaibhav Hiremath * Author: Vaibhav Hiremath <hvaibhav@ti.com> 5ed01e45cSVaibhav Hiremath * 6ed01e45cSVaibhav Hiremath * Based on omap3_evm_config.h 7ed01e45cSVaibhav Hiremath * 8ed01e45cSVaibhav Hiremath * Copyright (C) 2010 Texas Instruments Incorporated 9ed01e45cSVaibhav Hiremath * 101a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 11ed01e45cSVaibhav Hiremath */ 12ed01e45cSVaibhav Hiremath 13ed01e45cSVaibhav Hiremath #ifndef __CONFIG_H 14ed01e45cSVaibhav Hiremath #define __CONFIG_H 15ed01e45cSVaibhav Hiremath 163f53e619SDerald D. Woods #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 173f53e619SDerald D. Woods 181a5038caSVaibhav Hiremath #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 19ed01e45cSVaibhav Hiremath 203f53e619SDerald D. Woods /* 213f53e619SDerald D. Woods * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 223f53e619SDerald D. Woods * 64 bytes before this address should be set aside for u-boot.img's 233f53e619SDerald D. Woods * header. That is 0x800FFFC0--0x80100000 should not be used for any 243f53e619SDerald D. Woods * other needs. 253f53e619SDerald D. Woods */ 263f53e619SDerald D. Woods #define CONFIG_SYS_TEXT_BASE 0x80100000 273f53e619SDerald D. Woods #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 283f53e619SDerald D. Woods #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 293f53e619SDerald D. Woods 30ed01e45cSVaibhav Hiremath #include <asm/arch/cpu.h> /* get chip and board defs */ 31987ec585SNishanth Menon #include <asm/arch/omap.h> 32ed01e45cSVaibhav Hiremath 333f53e619SDerald D. Woods #define CONFIG_MISC_INIT_R 343f53e619SDerald D. Woods #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ 353f53e619SDerald D. Woods #define CONFIG_SETUP_MEMORY_TAGS 363f53e619SDerald D. Woods #define CONFIG_INITRD_TAG 373f53e619SDerald D. Woods #define CONFIG_REVISION_TAG 38ed01e45cSVaibhav Hiremath 39ed01e45cSVaibhav Hiremath /* Clock Defines */ 40ed01e45cSVaibhav Hiremath #define V_OSCK 26000000 /* Clock output from T2 */ 41ed01e45cSVaibhav Hiremath #define V_SCLK (V_OSCK >> 1) 42ed01e45cSVaibhav Hiremath 433f53e619SDerald D. Woods /* Size of malloc() pool */ 443f53e619SDerald D. Woods #define CONFIG_SYS_MALLOC_LEN (16 << 20) 45ed01e45cSVaibhav Hiremath 463f53e619SDerald D. Woods /* Hardware drivers */ 470a0db402SYegor Yefremov 483f53e619SDerald D. Woods /* NS16550 Configuration */ 49ed01e45cSVaibhav Hiremath #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 50ed01e45cSVaibhav Hiremath #define CONFIG_SYS_NS16550_SERIAL 51ed01e45cSVaibhav Hiremath #define CONFIG_SYS_NS16550_REG_SIZE (-4) 52ed01e45cSVaibhav Hiremath #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 53ed01e45cSVaibhav Hiremath 543f53e619SDerald D. Woods /* select serial console configuration */ 55ed01e45cSVaibhav Hiremath #define CONFIG_CONS_INDEX 3 56ed01e45cSVaibhav Hiremath #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 57ed01e45cSVaibhav Hiremath #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ 58ed01e45cSVaibhav Hiremath 59ed01e45cSVaibhav Hiremath /* allow to overwrite serial and ethaddr */ 60ed01e45cSVaibhav Hiremath #define CONFIG_ENV_OVERWRITE 61ed01e45cSVaibhav Hiremath #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 62ed01e45cSVaibhav Hiremath 115200} 633f53e619SDerald D. Woods 647dc27b05SAjay Kumar Gupta /* 657dc27b05SAjay Kumar Gupta * USB configuration 6695de1e2fSPaul Kocialkowski * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard 6795de1e2fSPaul Kocialkowski * Enable CONFIG_USB_MUSB_GADGET for Device functionalities. 687dc27b05SAjay Kumar Gupta */ 6988919ff7SIlya Yanok #define CONFIG_USB_MUSB_AM35X 7095de1e2fSPaul Kocialkowski #define CONFIG_USB_MUSB_PIO_ONLY 717dc27b05SAjay Kumar Gupta 7288919ff7SIlya Yanok #ifdef CONFIG_USB_MUSB_AM35X 737dc27b05SAjay Kumar Gupta 7495de1e2fSPaul Kocialkowski #ifdef CONFIG_USB_MUSB_HOST 757dc27b05SAjay Kumar Gupta 767dc27b05SAjay Kumar Gupta #ifdef CONFIG_USB_KEYBOARD 777dc27b05SAjay Kumar Gupta #define CONFIG_PREBOOT "usb start" 787dc27b05SAjay Kumar Gupta #endif /* CONFIG_USB_KEYBOARD */ 797dc27b05SAjay Kumar Gupta 8095de1e2fSPaul Kocialkowski #endif /* CONFIG_USB_MUSB_HOST */ 817dc27b05SAjay Kumar Gupta 8288919ff7SIlya Yanok #endif /* CONFIG_USB_MUSB_AM35X */ 837dc27b05SAjay Kumar Gupta 843f53e619SDerald D. Woods /* I2C */ 856789e84eSHeiko Schocher #define CONFIG_SYS_I2C 866789e84eSHeiko Schocher #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 876789e84eSHeiko Schocher #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 88ed01e45cSVaibhav Hiremath 893f53e619SDerald D. Woods /* Ethernet */ 9018a02e80STom Rini #define CONFIG_DRIVER_TI_EMAC 9118a02e80STom Rini #define CONFIG_DRIVER_TI_EMAC_USE_RMII 9218a02e80STom Rini #define CONFIG_MII 9318a02e80STom Rini #define CONFIG_BOOTP_DEFAULT 9418a02e80STom Rini #define CONFIG_BOOTP_DNS 9518a02e80STom Rini #define CONFIG_BOOTP_DNS2 9618a02e80STom Rini #define CONFIG_BOOTP_SEND_HOSTNAME 9718a02e80STom Rini #define CONFIG_NET_RETRY_COUNT 10 9818a02e80STom Rini 993f53e619SDerald D. Woods /* Board NAND Info. */ 1003f53e619SDerald D. Woods #ifdef CONFIG_NAND 101ed01e45cSVaibhav Hiremath #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 102ed01e45cSVaibhav Hiremath /* to access nand */ 1033f53e619SDerald D. Woods #define CONFIG_SYS_NAND_5_ADDR_CYCLE 1043f53e619SDerald D. Woods #define CONFIG_SYS_NAND_PAGE_COUNT 64 1053f53e619SDerald D. Woods #define CONFIG_SYS_NAND_PAGE_SIZE 2048 1063f53e619SDerald D. Woods #define CONFIG_SYS_NAND_OOBSIZE 64 1073f53e619SDerald D. Woods #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) 1083f53e619SDerald D. Woods #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 1093f53e619SDerald D. Woods #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \ 1103f53e619SDerald D. Woods 11, 12, 13, 14, 16, 17, 18, 19, 20, \ 1113f53e619SDerald D. Woods 21, 22, 23, 24, 25, 26, 27, 28, 30, \ 1123f53e619SDerald D. Woods 31, 32, 33, 34, 35, 36, 37, 38, 39, \ 1133f53e619SDerald D. Woods 40, 41, 42, 44, 45, 46, 47, 48, 49, \ 1143f53e619SDerald D. Woods 50, 51, 52, 53, 54, 55, 56 } 1153f53e619SDerald D. Woods 1163f53e619SDerald D. Woods #define CONFIG_SYS_NAND_ECCSIZE 512 1173f53e619SDerald D. Woods #define CONFIG_SYS_NAND_ECCBYTES 13 1183f53e619SDerald D. Woods #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW 1193f53e619SDerald D. Woods #define CONFIG_SYS_NAND_MAX_OOBFREE 2 1203f53e619SDerald D. Woods #define CONFIG_SYS_NAND_MAX_ECCPOS 56 1213f53e619SDerald D. Woods #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 1223f53e619SDerald D. Woods #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 1233f53e619SDerald D. Woods /* NAND block size is 128 KiB. Synchronize these values with 1243f53e619SDerald D. Woods * corresponding Device Tree entries in Linux: 1253f53e619SDerald D. Woods * MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000 1263f53e619SDerald D. Woods * U-Boot 15 * NAND_BLOCK_SIZE = 1920 KiB @ 0x080000 1273f53e619SDerald D. Woods * U-Boot environment 2 * NAND_BLOCK_SIZE = 256 KiB @ 0x260000 1283f53e619SDerald D. Woods * Kernel 64 * NAND_BLOCK_SIZE = 8 MiB @ 0x2A0000 1293f53e619SDerald D. Woods * DTB 4 * NAND_BLOCK_SIZE = 512 KiB @ 0xAA0000 1303f53e619SDerald D. Woods * RootFS Remaining Flash Space @ 0xB20000 1313f53e619SDerald D. Woods */ 1323f53e619SDerald D. Woods #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 1333f53e619SDerald D. Woods #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ 1343f53e619SDerald D. Woods "512k(MLO)," \ 1353f53e619SDerald D. Woods "1920k(u-boot)," \ 1363f53e619SDerald D. Woods "256k(u-boot-env)," \ 1373f53e619SDerald D. Woods "8m(kernel)," \ 1383f53e619SDerald D. Woods "512k(dtb)," \ 1393f53e619SDerald D. Woods "-(rootfs)" 1403f53e619SDerald D. Woods #else 1413f53e619SDerald D. Woods #define MTDIDS_DEFAULT 1423f53e619SDerald D. Woods #define MTDPARTS_DEFAULT 1433f53e619SDerald D. Woods #endif /* CONFIG_NAND */ 144ed01e45cSVaibhav Hiremath 145ed01e45cSVaibhav Hiremath /* Environment information */ 146ed01e45cSVaibhav Hiremath 147b3f44c21SJoe Hershberger #define CONFIG_BOOTFILE "uImage" 148ed01e45cSVaibhav Hiremath 149ed01e45cSVaibhav Hiremath #define CONFIG_EXTRA_ENV_SETTINGS \ 150ed01e45cSVaibhav Hiremath "loadaddr=0x82000000\0" \ 15149473adaSYegor Yefremov "console=ttyO2,115200n8\0" \ 15245776e36SDerald D. Woods "fdtfile=am3517-evm.dtb\0" \ 15345776e36SDerald D. Woods "fdtaddr=0x82C00000\0" \ 15445776e36SDerald D. Woods "vram=16M\0" \ 15545776e36SDerald D. Woods "bootenv=uEnv.txt\0" \ 15645776e36SDerald D. Woods "cmdline=\0" \ 15745776e36SDerald D. Woods "optargs=\0" \ 1583f53e619SDerald D. Woods "mtdids=" MTDIDS_DEFAULT "\0" \ 1593f53e619SDerald D. Woods "mtdparts=" MTDPARTS_DEFAULT "\0" \ 160122e6e0aSVaibhav Hiremath "mmcdev=0\0" \ 16145776e36SDerald D. Woods "mmcpart=1\0" \ 16245776e36SDerald D. Woods "mmcroot=/dev/mmcblk0p2 rw\0" \ 16345776e36SDerald D. Woods "mmcrootfstype=ext4 rootwait fixrtc\0" \ 164ed01e45cSVaibhav Hiremath "mmcargs=setenv bootargs console=${console} " \ 1653f53e619SDerald D. Woods "${mtdparts} " \ 16645776e36SDerald D. Woods "${optargs} " \ 16745776e36SDerald D. Woods "root=${mmcroot} " \ 16845776e36SDerald D. Woods "rootfstype=${mmcrootfstype} " \ 16945776e36SDerald D. Woods "${cmdline}\0" \ 170ed01e45cSVaibhav Hiremath "nandargs=setenv bootargs console=${console} " \ 1713f53e619SDerald D. Woods "${mtdparts} " \ 1723f53e619SDerald D. Woods "${optargs} " \ 1733f53e619SDerald D. Woods "root=ubi0:rootfs rw ubi.mtd=rootfs " \ 1743f53e619SDerald D. Woods "rootfstype=ubifs rootwait " \ 1753f53e619SDerald D. Woods "${cmdline}\0" \ 17645776e36SDerald D. Woods "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootenv}\0"\ 17745776e36SDerald D. Woods "importbootenv=echo Importing environment from mmc ...; " \ 17845776e36SDerald D. Woods "env import -t ${loadaddr} ${filesize}\0" \ 179ed01e45cSVaibhav Hiremath "bootscript=echo Running bootscript from mmc ...; " \ 180ed01e45cSVaibhav Hiremath "source ${loadaddr}\0" \ 18145776e36SDerald D. Woods "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootfile}\0" \ 18245776e36SDerald D. Woods "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}\0" \ 183ed01e45cSVaibhav Hiremath "mmcboot=echo Booting from mmc ...; " \ 184ed01e45cSVaibhav Hiremath "run mmcargs; " \ 18545776e36SDerald D. Woods "bootz ${loadaddr} - ${fdtaddr}\0" \ 186ed01e45cSVaibhav Hiremath "nandboot=echo Booting from nand ...; " \ 187ed01e45cSVaibhav Hiremath "run nandargs; " \ 1883f53e619SDerald D. Woods "nand read ${loadaddr} 2a0000 800000; " \ 1893f53e619SDerald D. Woods "nand read ${fdtaddr} aa0000 80000; " \ 1903f53e619SDerald D. Woods "bootm ${loadaddr} - ${fdtaddr}\0" \ 191ed01e45cSVaibhav Hiremath 192ed01e45cSVaibhav Hiremath #define CONFIG_BOOTCOMMAND \ 19366968110SAndrew Bradford "mmc dev ${mmcdev}; if mmc rescan; then " \ 19445776e36SDerald D. Woods "echo SD/MMC found on device $mmcdev; " \ 19545776e36SDerald D. Woods "if run loadbootenv; then " \ 19645776e36SDerald D. Woods "run importbootenv; " \ 197ed01e45cSVaibhav Hiremath "fi; " \ 19845776e36SDerald D. Woods "echo Checking if uenvcmd is set ...; " \ 19945776e36SDerald D. Woods "if test -n $uenvcmd; then " \ 20045776e36SDerald D. Woods "echo Running uenvcmd ...; " \ 20145776e36SDerald D. Woods "run uenvcmd; " \ 20245776e36SDerald D. Woods "fi; " \ 20345776e36SDerald D. Woods "echo Running default loadimage ...; " \ 20445776e36SDerald D. Woods "setenv bootfile zImage; " \ 20545776e36SDerald D. Woods "if run loadimage; then " \ 20645776e36SDerald D. Woods "run loadfdt; " \ 20745776e36SDerald D. Woods "run mmcboot; " \ 208ed01e45cSVaibhav Hiremath "fi; " \ 209ed01e45cSVaibhav Hiremath "else run nandboot; fi" 210ed01e45cSVaibhav Hiremath 2113f53e619SDerald D. Woods /* Miscellaneous configurable options */ 2123f53e619SDerald D. Woods #define CONFIG_AUTO_COMPLETE 2133f53e619SDerald D. Woods #define CONFIG_CMDLINE_EDITING 2143f53e619SDerald D. Woods #define CONFIG_SYS_LONGHELP 2153f53e619SDerald D. Woods 2163f53e619SDerald D. Woods /* We set the max number of command args high to avoid HUSH bugs. */ 2173f53e619SDerald D. Woods #define CONFIG_SYS_MAXARGS 64 2183f53e619SDerald D. Woods 2193f53e619SDerald D. Woods /* Console I/O Buffer Size */ 2203f53e619SDerald D. Woods #define CONFIG_SYS_CBSIZE 512 2213f53e619SDerald D. Woods 222ed01e45cSVaibhav Hiremath /* memtest works on */ 223ed01e45cSVaibhav Hiremath #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 224ed01e45cSVaibhav Hiremath #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 225ed01e45cSVaibhav Hiremath 0x01F00000) /* 31MB */ 226ed01e45cSVaibhav Hiremath 227ed01e45cSVaibhav Hiremath #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 228ed01e45cSVaibhav Hiremath /* address */ 229ed01e45cSVaibhav Hiremath 230ed01e45cSVaibhav Hiremath /* 231ed01e45cSVaibhav Hiremath * AM3517 has 12 GP timers, they can be driven by the system clock 232ed01e45cSVaibhav Hiremath * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 233ed01e45cSVaibhav Hiremath * This rate is divided by a local divisor. 234ed01e45cSVaibhav Hiremath */ 235ed01e45cSVaibhav Hiremath #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 236ed01e45cSVaibhav Hiremath #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 237ed01e45cSVaibhav Hiremath 2383f53e619SDerald D. Woods /* Physical Memory Map */ 239ed01e45cSVaibhav Hiremath #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 240ed01e45cSVaibhav Hiremath #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 2413f53e619SDerald D. Woods #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 2423f53e619SDerald D. Woods #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 2433f53e619SDerald D. Woods #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 2443f53e619SDerald D. Woods #define CONFIG_SYS_INIT_RAM_SIZE 0x800 2453f53e619SDerald D. Woods #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 2463f53e619SDerald D. Woods CONFIG_SYS_INIT_RAM_SIZE - \ 2473f53e619SDerald D. Woods GENERATED_GBL_DATA_SIZE) 248ed01e45cSVaibhav Hiremath 2493f53e619SDerald D. Woods /* FLASH and environment organization */ 250ed01e45cSVaibhav Hiremath 251ed01e45cSVaibhav Hiremath /* **** PISMO SUPPORT *** */ 252ed01e45cSVaibhav Hiremath #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 253ed01e45cSVaibhav Hiremath /* on one chip */ 254ed01e45cSVaibhav Hiremath #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 255ed01e45cSVaibhav Hiremath #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 256ed01e45cSVaibhav Hiremath 2573f53e619SDerald D. Woods #if defined(CONFIG_NAND) 258222a3113Spekon gupta #define CONFIG_SYS_FLASH_BASE NAND_BASE 2596cbec7b3SLuca Ceresoli #endif 260ed01e45cSVaibhav Hiremath 261ed01e45cSVaibhav Hiremath /* Monitor at start of flash */ 262ed01e45cSVaibhav Hiremath #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 263ed01e45cSVaibhav Hiremath 2646cbec7b3SLuca Ceresoli #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 2653f53e619SDerald D. Woods #define CONFIG_ENV_SIZE CONFIG_SYS_ENV_SECT_SIZE 2663f53e619SDerald D. Woods #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 2676cbec7b3SLuca Ceresoli #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 2686cbec7b3SLuca Ceresoli #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 2695059a2a4STom Rini 2705059a2a4STom Rini /* Defines for SPL */ 27147f7bcaeSTom Rini #define CONFIG_SPL_FRAMEWORK 2725059a2a4STom Rini #define CONFIG_SPL_NAND_SIMPLE 273138daa7bSDerald D. Woods #define CONFIG_SPL_TEXT_BASE 0x40200000 274*fa2f81b0STom Rini #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 275*fa2f81b0STom Rini CONFIG_SPL_TEXT_BASE) 2765059a2a4STom Rini 2775059a2a4STom Rini #define CONFIG_SPL_BSS_START_ADDR 0x80000000 2785059a2a4STom Rini #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 2795059a2a4STom Rini 280e2ccdf89SPaul Kocialkowski #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 281205b4f33SGuillaume GARDET #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 2825059a2a4STom Rini 2836f2f01b9SScott Wood #define CONFIG_SPL_NAND_BASE 2846f2f01b9SScott Wood #define CONFIG_SPL_NAND_DRIVERS 2856f2f01b9SScott Wood #define CONFIG_SPL_NAND_ECC 2865059a2a4STom Rini 287ed01e45cSVaibhav Hiremath #endif /* __CONFIG_H */ 288