1 /* 2 * am3517_crane.h - Default configuration for AM3517 CraneBoard. 3 * 4 * Author: Srinath.R <srinath@mistralsolutions.com> 5 * 6 * Based on include/configs/am3517evm.h 7 * 8 * Copyright (C) 2011 Mistral Solutions pvt Ltd 9 * 10 * SPDX-License-Identifier: GPL-2.0+ 11 */ 12 13 #ifndef __CONFIG_H 14 #define __CONFIG_H 15 16 /* 17 * High Level Configuration Options 18 */ 19 #define CONFIG_OMAP3_AM3517CRANE 1 /* working with CRANEBOARD */ 20 21 #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ 22 23 #include <asm/arch/cpu.h> /* get chip and board defs */ 24 #include <asm/arch/omap.h> 25 26 /* Clock Defines */ 27 #define V_OSCK 26000000 /* Clock output from T2 */ 28 #define V_SCLK (V_OSCK >> 1) 29 30 #define CONFIG_MISC_INIT_R 31 32 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ 33 #define CONFIG_SETUP_MEMORY_TAGS 1 34 #define CONFIG_INITRD_TAG 1 35 #define CONFIG_REVISION_TAG 1 36 37 /* 38 * Size of malloc() pool 39 */ 40 #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ 41 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) 42 /* initial data */ 43 /* 44 * DDR related 45 */ 46 #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) 47 48 /* 49 * Hardware drivers 50 */ 51 52 /* 53 * NS16550 Configuration 54 */ 55 #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ 56 57 #define CONFIG_SYS_NS16550_SERIAL 58 #define CONFIG_SYS_NS16550_REG_SIZE (-4) 59 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK 60 61 /* 62 * select serial console configuration 63 */ 64 #define CONFIG_CONS_INDEX 3 65 #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 66 #define CONFIG_SERIAL3 3 /* UART3 on CRANEBOARD */ 67 68 /* allow to overwrite serial and ethaddr */ 69 #define CONFIG_ENV_OVERWRITE 70 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ 71 115200} 72 73 /* 74 * USB configuration 75 * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard 76 * Enable CONFIG_USB_MUSB_UDC for Device functionalities. 77 */ 78 #define CONFIG_USB_AM35X 1 79 #define CONFIG_USB_MUSB_HCD 1 80 81 #ifdef CONFIG_USB_AM35X 82 83 #ifdef CONFIG_USB_MUSB_HCD 84 85 #ifdef CONFIG_USB_KEYBOARD 86 #define CONFIG_SYS_USB_EVENT_POLL 87 #define CONFIG_PREBOOT "usb start" 88 #endif /* CONFIG_USB_KEYBOARD */ 89 90 #endif /* CONFIG_USB_MUSB_HCD */ 91 92 #ifdef CONFIG_USB_MUSB_UDC 93 /* USB device configuration */ 94 #define CONFIG_USB_DEVICE 1 95 #define CONFIG_USB_TTY 1 96 /* Change these to suit your needs */ 97 #define CONFIG_USBD_VENDORID 0x0451 98 #define CONFIG_USBD_PRODUCTID 0x5678 99 #define CONFIG_USBD_MANUFACTURER "Texas Instruments" 100 #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE" 101 #endif /* CONFIG_USB_MUSB_UDC */ 102 103 #endif /* CONFIG_USB_AM35X */ 104 105 /* commands to include */ 106 #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ 107 108 #define CONFIG_CMD_NAND /* NAND support */ 109 110 #define CONFIG_SYS_I2C 111 #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 112 #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 113 #define CONFIG_SYS_I2C_OMAP34XX 114 115 /* 116 * Board NAND Info. 117 */ 118 #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ 119 /* to access nand */ 120 #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ 121 /* to access */ 122 /* nand at CS0 */ 123 124 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ 125 /* NAND devices */ 126 127 #define CONFIG_JFFS2_NAND 128 /* nand device jffs2 lives on */ 129 #define CONFIG_JFFS2_DEV "nand0" 130 /* start of jffs2 partition */ 131 #define CONFIG_JFFS2_PART_OFFSET 0x680000 132 #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ 133 134 /* Environment information */ 135 136 #define CONFIG_BOOTFILE "uImage" 137 138 #define CONFIG_EXTRA_ENV_SETTINGS \ 139 "loadaddr=0x82000000\0" \ 140 "console=ttyS2,115200n8\0" \ 141 "mmcdev=0\0" \ 142 "mmcargs=setenv bootargs console=${console} " \ 143 "root=/dev/mmcblk0p2 rw " \ 144 "rootfstype=ext3 rootwait\0" \ 145 "nandargs=setenv bootargs console=${console} " \ 146 "root=/dev/mtdblock4 rw " \ 147 "rootfstype=jffs2\0" \ 148 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ 149 "bootscript=echo Running bootscript from mmc ...; " \ 150 "source ${loadaddr}\0" \ 151 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ 152 "mmcboot=echo Booting from mmc ...; " \ 153 "run mmcargs; " \ 154 "bootm ${loadaddr}\0" \ 155 "nandboot=echo Booting from nand ...; " \ 156 "run nandargs; " \ 157 "nand read ${loadaddr} 280000 400000; " \ 158 "bootm ${loadaddr}\0" \ 159 160 #define CONFIG_BOOTCOMMAND \ 161 "mmc dev ${mmcdev}; if mmc rescan; then " \ 162 "if run loadbootscript; then " \ 163 "run bootscript; " \ 164 "else " \ 165 "if run loaduimage; then " \ 166 "run mmcboot; " \ 167 "else run nandboot; " \ 168 "fi; " \ 169 "fi; " \ 170 "else run nandboot; fi" 171 172 #define CONFIG_AUTO_COMPLETE 1 173 /* 174 * Miscellaneous configurable options 175 */ 176 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 177 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 178 /* Print Buffer Size */ 179 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 180 sizeof(CONFIG_SYS_PROMPT) + 16) 181 #define CONFIG_SYS_MAXARGS 32 /* max number of command */ 182 /* args */ 183 /* Boot Argument Buffer Size */ 184 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) 185 /* memtest works on */ 186 #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) 187 #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ 188 0x01F00000) /* 31MB */ 189 190 #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ 191 /* address */ 192 193 /* 194 * AM3517 has 12 GP timers, they can be driven by the system clock 195 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). 196 * This rate is divided by a local divisor. 197 */ 198 #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 199 #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ 200 201 /*----------------------------------------------------------------------- 202 * Physical Memory Map 203 */ 204 #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ 205 #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 206 #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 207 208 /*----------------------------------------------------------------------- 209 * FLASH and environment organization 210 */ 211 212 /* **** PISMO SUPPORT *** */ 213 #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ 214 /* on one chip */ 215 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ 216 #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ 217 218 #define CONFIG_SYS_FLASH_BASE NAND_BASE 219 220 /* Monitor at start of flash */ 221 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 222 223 #define CONFIG_NAND_OMAP_GPMC 224 #define CONFIG_ENV_IS_IN_NAND 1 225 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ 226 227 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */ 228 #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET 229 #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET 230 231 /*----------------------------------------------------------------------- 232 * CFI FLASH driver setup 233 */ 234 /* timeout values are in ticks */ 235 #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) 236 #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) 237 238 /* Flash banks JFFS2 should use */ 239 #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ 240 CONFIG_SYS_MAX_NAND_DEVICE) 241 #define CONFIG_SYS_JFFS2_MEM_NAND 242 /* use flash_info[2] */ 243 #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS 244 #define CONFIG_SYS_JFFS2_NUM_BANKS 1 245 246 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 247 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 248 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 249 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ 250 CONFIG_SYS_INIT_RAM_SIZE - \ 251 GENERATED_GBL_DATA_SIZE) 252 253 /* Defines for SPL */ 254 #define CONFIG_SPL_FRAMEWORK 255 #define CONFIG_SPL_BOARD_INIT 256 #define CONFIG_SPL_NAND_SIMPLE 257 #define CONFIG_SPL_TEXT_BASE 0x40200800 258 #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ 259 CONFIG_SPL_TEXT_BASE) 260 261 #define CONFIG_SPL_BSS_START_ADDR 0x80000000 262 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ 263 264 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 265 #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" 266 267 #define CONFIG_SPL_NAND_BASE 268 #define CONFIG_SPL_NAND_DRIVERS 269 #define CONFIG_SPL_NAND_ECC 270 #define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds" 271 272 /* NAND boot config */ 273 #define CONFIG_SYS_NAND_BUSWIDTH_16BIT 274 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 275 #define CONFIG_SYS_NAND_PAGE_COUNT 64 276 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 277 #define CONFIG_SYS_NAND_OOBSIZE 64 278 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 279 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 280 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 281 10, 11, 12, 13} 282 #define CONFIG_SYS_NAND_ECCSIZE 512 283 #define CONFIG_SYS_NAND_ECCBYTES 3 284 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW 285 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 286 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 287 288 /* 289 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM 290 * 64 bytes before this address should be set aside for u-boot.img's 291 * header. That is 0x800FFFC0--0x80100000 should not be used for any 292 * other needs. 293 */ 294 #define CONFIG_SYS_TEXT_BASE 0x80100000 295 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 296 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 297 298 #endif /* __CONFIG_H */ 299