1*9d1b2987SEnric Balletbò i Serra /* 2*9d1b2987SEnric Balletbò i Serra * am335x_sl50.h 3*9d1b2987SEnric Balletbò i Serra * 4*9d1b2987SEnric Balletbò i Serra * Copyright (C) 2015 Toby Churchill Ltd - http://www.toby-churchill.com/ 5*9d1b2987SEnric Balletbò i Serra * 6*9d1b2987SEnric Balletbò i Serra * SPDX-License-Identifier: GPL-2.0+ 7*9d1b2987SEnric Balletbò i Serra */ 8*9d1b2987SEnric Balletbò i Serra 9*9d1b2987SEnric Balletbò i Serra #ifndef __CONFIG_AM335X_EVM_H 10*9d1b2987SEnric Balletbò i Serra #define __CONFIG_AM335X_EVM_H 11*9d1b2987SEnric Balletbò i Serra 12*9d1b2987SEnric Balletbò i Serra #include <configs/ti_am335x_common.h> 13*9d1b2987SEnric Balletbò i Serra 14*9d1b2987SEnric Balletbò i Serra #ifndef CONFIG_SPL_BUILD 15*9d1b2987SEnric Balletbò i Serra # define CONFIG_TIMESTAMP 16*9d1b2987SEnric Balletbò i Serra #endif 17*9d1b2987SEnric Balletbò i Serra 18*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_BOOTM_LEN (16 << 20) 19*9d1b2987SEnric Balletbò i Serra 20*9d1b2987SEnric Balletbò i Serra /*#define CONFIG_MACH_TYPE 3589 Until the next sync */ 21*9d1b2987SEnric Balletbò i Serra 22*9d1b2987SEnric Balletbò i Serra /* Clock Defines */ 23*9d1b2987SEnric Balletbò i Serra #define V_OSCK 24000000 /* Clock output from T2 */ 24*9d1b2987SEnric Balletbò i Serra #define V_SCLK (V_OSCK) 25*9d1b2987SEnric Balletbò i Serra 26*9d1b2987SEnric Balletbò i Serra /* Always 128 KiB env size */ 27*9d1b2987SEnric Balletbò i Serra #define CONFIG_ENV_SIZE (128 << 10) 28*9d1b2987SEnric Balletbò i Serra 29*9d1b2987SEnric Balletbò i Serra #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 30*9d1b2987SEnric Balletbò i Serra 31*9d1b2987SEnric Balletbò i Serra #ifndef CONFIG_SPL_BUILD 32*9d1b2987SEnric Balletbò i Serra 33*9d1b2987SEnric Balletbò i Serra #include <config_distro_defaults.h> 34*9d1b2987SEnric Balletbò i Serra 35*9d1b2987SEnric Balletbò i Serra #define MEM_LAYOUT_ENV_SETTINGS \ 36*9d1b2987SEnric Balletbò i Serra "scriptaddr=0x80000000\0" \ 37*9d1b2987SEnric Balletbò i Serra "pxefile_addr_r=0x80100000\0" \ 38*9d1b2987SEnric Balletbò i Serra "kernel_addr_r=0x82000000\0" \ 39*9d1b2987SEnric Balletbò i Serra "fdt_addr_r=0x88000000\0" \ 40*9d1b2987SEnric Balletbò i Serra "ramdisk_addr_r=0x88080000\0" \ 41*9d1b2987SEnric Balletbò i Serra 42*9d1b2987SEnric Balletbò i Serra #define BOOT_TARGET_DEVICES(func) \ 43*9d1b2987SEnric Balletbò i Serra func(MMC, mmc, 0) \ 44*9d1b2987SEnric Balletbò i Serra func(MMC, mmc, 1) 45*9d1b2987SEnric Balletbò i Serra 46*9d1b2987SEnric Balletbò i Serra #define AM335XX_BOARD_FDTFILE \ 47*9d1b2987SEnric Balletbò i Serra "fdtfile=am335x-sl50.dtb\0" \ 48*9d1b2987SEnric Balletbò i Serra 49*9d1b2987SEnric Balletbò i Serra #include <config_distro_bootcmd.h> 50*9d1b2987SEnric Balletbò i Serra 51*9d1b2987SEnric Balletbò i Serra #define CONFIG_EXTRA_ENV_SETTINGS \ 52*9d1b2987SEnric Balletbò i Serra AM335XX_BOARD_FDTFILE \ 53*9d1b2987SEnric Balletbò i Serra MEM_LAYOUT_ENV_SETTINGS \ 54*9d1b2987SEnric Balletbò i Serra BOOTENV 55*9d1b2987SEnric Balletbò i Serra 56*9d1b2987SEnric Balletbò i Serra #endif 57*9d1b2987SEnric Balletbò i Serra 58*9d1b2987SEnric Balletbò i Serra /* NS16550 Configuration */ 59*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ 60*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ 61*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ 62*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ 63*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ 64*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ 65*9d1b2987SEnric Balletbò i Serra 66*9d1b2987SEnric Balletbò i Serra #define CONFIG_ENV_EEPROM_IS_ON_I2C 67*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ 68*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 69*9d1b2987SEnric Balletbò i Serra 70*9d1b2987SEnric Balletbò i Serra /* PMIC support */ 71*9d1b2987SEnric Balletbò i Serra #define CONFIG_POWER_TPS65217 72*9d1b2987SEnric Balletbò i Serra #define CONFIG_POWER_TPS65910 73*9d1b2987SEnric Balletbò i Serra 74*9d1b2987SEnric Balletbò i Serra /* SPL */ 75*9d1b2987SEnric Balletbò i Serra 76*9d1b2987SEnric Balletbò i Serra /* Bootcount using the RTC block */ 77*9d1b2987SEnric Balletbò i Serra #define CONFIG_BOOTCOUNT_LIMIT 78*9d1b2987SEnric Balletbò i Serra #define CONFIG_BOOTCOUNT_AM33XX 79*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_BOOTCOUNT_BE 80*9d1b2987SEnric Balletbò i Serra 81*9d1b2987SEnric Balletbò i Serra #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) 82*9d1b2987SEnric Balletbò i Serra /* Remove other SPL modes. */ 83*9d1b2987SEnric Balletbò i Serra /* disable host part of MUSB in SPL */ 84*9d1b2987SEnric Balletbò i Serra #undef CONFIG_MUSB_HOST 85*9d1b2987SEnric Balletbò i Serra /* disable EFI partitions and partition UUID support */ 86*9d1b2987SEnric Balletbò i Serra #endif 87*9d1b2987SEnric Balletbò i Serra 88*9d1b2987SEnric Balletbò i Serra #if defined(CONFIG_EMMC_BOOT) 89*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_MMC_ENV_DEV 1 90*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_MMC_ENV_PART 2 91*9d1b2987SEnric Balletbò i Serra #define CONFIG_ENV_OFFSET 0x0 92*9d1b2987SEnric Balletbò i Serra #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 93*9d1b2987SEnric Balletbò i Serra #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 94*9d1b2987SEnric Balletbò i Serra #endif 95*9d1b2987SEnric Balletbò i Serra 96*9d1b2987SEnric Balletbò i Serra /* Network. */ 97*9d1b2987SEnric Balletbò i Serra #define CONFIG_PHY_SMSC 98*9d1b2987SEnric Balletbò i Serra 99*9d1b2987SEnric Balletbò i Serra #endif /* ! __CONFIG_AM335X_SL50_H */ 100