xref: /rk3399_rockchip-uboot/include/configs/alt.h (revision ef97b6ed89f52c3a39777f710081eb53f9496086)
1 /*
2  * include/configs/alt.h
3  *     This file is alt board configuration.
4  *
5  * Copyright (C) 2014 Renesas Electronics Corporation
6  *
7  * SPDX-License-Identifier: GPL-2.0
8  */
9 
10 #ifndef __ALT_H
11 #define __ALT_H
12 
13 #undef DEBUG
14 #define CONFIG_ARMV7
15 #define CONFIG_R8A7794
16 #define CONFIG_RMOBILE_BOARD_STRING "Alt"
17 #define CONFIG_SH_GPIO_PFC
18 
19 #include <asm/arch/rmobile.h>
20 
21 #define	CONFIG_CMD_EDITENV
22 #define	CONFIG_CMD_SAVEENV
23 #define CONFIG_CMD_MEMORY
24 #define CONFIG_CMD_DFL
25 #define CONFIG_CMD_SDRAM
26 #define CONFIG_CMD_RUN
27 #define CONFIG_CMD_LOADS
28 #define CONFIG_CMD_NET
29 #define CONFIG_CMD_MII
30 #define CONFIG_CMD_PING
31 #define CONFIG_CMD_DHCP
32 #define CONFIG_CMD_NFS
33 #define CONFIG_CMD_BOOTZ
34 #define CONFIG_CMD_SF
35 #define CONFIG_CMD_SPI
36 
37 #if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
38 #define CONFIG_SYS_TEXT_BASE	0x70000000
39 #else
40 #define CONFIG_SYS_TEXT_BASE	0xE6304000
41 #endif
42 #define CONFIG_SYS_THUMB_BUILD
43 #define CONFIG_SYS_GENERIC_BOARD
44 
45 #define	CONFIG_CMDLINE_TAG
46 #define	CONFIG_SETUP_MEMORY_TAGS
47 #define	CONFIG_INITRD_TAG
48 #define	CONFIG_CMDLINE_EDITING
49 
50 #define CONFIG_OF_LIBFDT
51 #define BOARD_LATE_INIT
52 
53 #define CONFIG_BAUDRATE		38400
54 #define CONFIG_BOOTDELAY	3
55 #define CONFIG_BOOTARGS		""
56 
57 #define CONFIG_VERSION_VARIABLE
58 #undef	CONFIG_SHOW_BOOT_PROGRESS
59 
60 #define CONFIG_ARCH_CPU_INIT
61 #define CONFIG_DISPLAY_CPUINFO
62 #define CONFIG_DISPLAY_BOARDINFO
63 #define CONFIG_BOARD_EARLY_INIT_F
64 #define CONFIG_TMU_TIMER
65 
66 #if defined(CONFIG_RMOBILE_EXTRAM_BOOT)
67 #define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
68 #else
69 #define CONFIG_SYS_INIT_SP_ADDR		0xE633FFFC
70 #endif
71 #define STACK_AREA_SIZE			0xC000
72 #define LOW_LEVEL_MERAM_STACK \
73 		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
74 
75 /* MEMORY */
76 #define ALT_SDRAM_BASE		0x40000000
77 #define ALT_SDRAM_SIZE		(1024u * 1024 * 1024)
78 #define ALT_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)
79 
80 #define CONFIG_SYS_LONGHELP
81 #define CONFIG_SYS_CBSIZE		256
82 #define CONFIG_SYS_PBSIZE		256
83 #define CONFIG_SYS_MAXARGS		16
84 #define CONFIG_SYS_BARGSIZE		512
85 #define CONFIG_SYS_BAUDRATE_TABLE	{ 38400, 115200 }
86 
87 /* SCIF */
88 #define CONFIG_SCIF_CONSOLE
89 #define CONFIG_CONS_SCIF2
90 #undef	CONFIG_SYS_CONSOLE_INFO_QUIET
91 #undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
92 #undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE
93 
94 #define CONFIG_SYS_MEMTEST_START	(ALT_SDRAM_BASE)
95 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
96 					 504 * 1024 * 1024)
97 #undef	CONFIG_SYS_ALT_MEMTEST
98 #undef	CONFIG_SYS_MEMTEST_SCRATCH
99 #undef	CONFIG_SYS_LOADS_BAUD_CHANGE
100 
101 #define CONFIG_SYS_SDRAM_BASE		(ALT_SDRAM_BASE)
102 #define CONFIG_SYS_SDRAM_SIZE		(ALT_UBOOT_SDRAM_SIZE)
103 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x7fc0)
104 #define CONFIG_NR_DRAM_BANKS		1
105 
106 #define CONFIG_SYS_MONITOR_BASE		0x00000000
107 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
108 #define CONFIG_SYS_MALLOC_LEN		(1 * 1024 * 1024)
109 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
110 
111 /* FLASH */
112 #define CONFIG_SPI
113 #define CONFIG_SPI_FLASH_BAR
114 #define CONFIG_SH_QSPI
115 #define CONFIG_SPI_FLASH
116 #define CONFIG_SPI_FLASH_SPANSION
117 #define CONFIG_SPI_FLASH_QUAD
118 #define CONFIG_SYS_NO_FLASH
119 
120 /* ENV setting */
121 #define CONFIG_ENV_IS_IN_SPI_FLASH
122 #define CONFIG_ENV_SECT_SIZE	(256 * 1024)
123 #define CONFIG_ENV_ADDR		0xC0000
124 #define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
125 #define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
126 
127 #define CONFIG_EXTRA_ENV_SETTINGS \
128 	"bootm_low=0x40e00000\0" \
129 	"bootm_size=0x100000\0" \
130 
131 /* SH Ether */
132 #define	CONFIG_NET_MULTI
133 #define CONFIG_SH_ETHER
134 #define CONFIG_SH_ETHER_USE_PORT	0
135 #define CONFIG_SH_ETHER_PHY_ADDR	0x1
136 #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
137 #define CONFIG_SH_ETHER_CACHE_WRITEBACK
138 #define CONFIG_SH_ETHER_CACHE_INVALIDATE
139 #define CONFIG_SH_ETHER_ALIGNE_SIZE 64
140 #define CONFIG_PHYLIB
141 #define CONFIG_PHY_MICREL
142 #define CONFIG_BITBANGMII
143 #define CONFIG_BITBANGMII_MULTI
144 
145 /* Board Clock */
146 #define RMOBILE_XTAL_CLK        20000000u
147 #define CONFIG_SYS_CLK_FREQ     RMOBILE_XTAL_CLK
148 #define CONFIG_SH_TMU_CLK_FREQ  (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
149 #define CONFIG_PLL1_CLK_FREQ    (CONFIG_SYS_CLK_FREQ * 156 / 2)
150 #define CONFIG_P_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 24)
151 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_P_CLK_FREQ
152 
153 #define CONFIG_SYS_TMU_CLK_DIV  4
154 
155 /* i2c */
156 #define CONFIG_CMD_I2C
157 #define CONFIG_SYS_I2C
158 #define CONFIG_SYS_I2C_SH
159 #define CONFIG_SYS_I2C_SLAVE		0x7F
160 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS       3
161 #define CONFIG_SYS_I2C_SH_BASE0		0xE6500000
162 #define CONFIG_SYS_I2C_SH_SPEED0	400000
163 #define CONFIG_SYS_I2C_SH_BASE1		0xE6510000
164 #define CONFIG_SYS_I2C_SH_SPEED1	400000
165 #define CONFIG_SYS_I2C_SH_BASE2		0xE60B0000
166 #define CONFIG_SYS_I2C_SH_SPEED2	400000
167 #define CONFIG_SH_I2C_DATA_HIGH		4
168 #define CONFIG_SH_I2C_DATA_LOW		5
169 #define CONFIG_SH_I2C_CLOCK		10000000
170 
171 #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
172 
173 #endif /* __ALT_H */
174