1cff2f5f0SNobuhiro Iwamatsu /* 2cff2f5f0SNobuhiro Iwamatsu * include/configs/alt.h 3cff2f5f0SNobuhiro Iwamatsu * This file is alt board configuration. 4cff2f5f0SNobuhiro Iwamatsu * 5cff2f5f0SNobuhiro Iwamatsu * Copyright (C) 2014 Renesas Electronics Corporation 6cff2f5f0SNobuhiro Iwamatsu * 7cff2f5f0SNobuhiro Iwamatsu * SPDX-License-Identifier: GPL-2.0 8cff2f5f0SNobuhiro Iwamatsu */ 9cff2f5f0SNobuhiro Iwamatsu 10cff2f5f0SNobuhiro Iwamatsu #ifndef __ALT_H 11cff2f5f0SNobuhiro Iwamatsu #define __ALT_H 12cff2f5f0SNobuhiro Iwamatsu 13cff2f5f0SNobuhiro Iwamatsu #undef DEBUG 14cff2f5f0SNobuhiro Iwamatsu #define CONFIG_R8A7794 15*1cc95f6eSNobuhiro Iwamatsu #define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt" 16cff2f5f0SNobuhiro Iwamatsu 175ca6dfe6SNobuhiro Iwamatsu #include "rcar-gen2-common.h" 18cff2f5f0SNobuhiro Iwamatsu 19*1cc95f6eSNobuhiro Iwamatsu #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 20c9b59bf7SNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0x70000000 21c9b59bf7SNobuhiro Iwamatsu #else 22cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_TEXT_BASE 0xE6304000 23c9b59bf7SNobuhiro Iwamatsu #endif 24cff2f5f0SNobuhiro Iwamatsu 25*1cc95f6eSNobuhiro Iwamatsu #if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT) 26c9b59bf7SNobuhiro Iwamatsu #define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC 27c9b59bf7SNobuhiro Iwamatsu #else 28cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC 29c9b59bf7SNobuhiro Iwamatsu #endif 30cff2f5f0SNobuhiro Iwamatsu #define STACK_AREA_SIZE 0xC000 31cff2f5f0SNobuhiro Iwamatsu #define LOW_LEVEL_MERAM_STACK \ 32cff2f5f0SNobuhiro Iwamatsu (CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4) 33cff2f5f0SNobuhiro Iwamatsu 34cff2f5f0SNobuhiro Iwamatsu /* MEMORY */ 355ca6dfe6SNobuhiro Iwamatsu #define RCAR_GEN2_SDRAM_BASE 0x40000000 365ca6dfe6SNobuhiro Iwamatsu #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) 375ca6dfe6SNobuhiro Iwamatsu #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024) 38cff2f5f0SNobuhiro Iwamatsu 39cff2f5f0SNobuhiro Iwamatsu /* SCIF */ 40cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SCIF_CONSOLE 41cff2f5f0SNobuhiro Iwamatsu 42cff2f5f0SNobuhiro Iwamatsu /* FLASH */ 43cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SPI 44cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_QSPI 45cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SPI_FLASH_QUAD 46cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_NO_FLASH 47cff2f5f0SNobuhiro Iwamatsu 48cff2f5f0SNobuhiro Iwamatsu /* SH Ether */ 49cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER 50cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_USE_PORT 0 51cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_ADDR 0x1 52cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII 53cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_CACHE_WRITEBACK 54cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_CACHE_INVALIDATE 55cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_ETHER_ALIGNE_SIZE 64 56cff2f5f0SNobuhiro Iwamatsu #define CONFIG_PHYLIB 57cff2f5f0SNobuhiro Iwamatsu #define CONFIG_PHY_MICREL 58cff2f5f0SNobuhiro Iwamatsu #define CONFIG_BITBANGMII 59cff2f5f0SNobuhiro Iwamatsu #define CONFIG_BITBANGMII_MULTI 60cff2f5f0SNobuhiro Iwamatsu 61cff2f5f0SNobuhiro Iwamatsu /* Board Clock */ 62cff2f5f0SNobuhiro Iwamatsu #define RMOBILE_XTAL_CLK 20000000u 63cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK 64cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */ 65cff2f5f0SNobuhiro Iwamatsu #define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2) 66cff2f5f0SNobuhiro Iwamatsu #define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24) 67cff2f5f0SNobuhiro Iwamatsu 68cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_TMU_CLK_DIV 4 69cff2f5f0SNobuhiro Iwamatsu 70cff2f5f0SNobuhiro Iwamatsu /* i2c */ 71cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C 72cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH 73cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SLAVE 0x7F 74cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3 75cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_SPEED0 400000 76cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_SPEED1 400000 77cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_SH_SPEED2 400000 78cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_I2C_DATA_HIGH 4 79cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_I2C_DATA_LOW 5 80cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SH_I2C_CLOCK 10000000 81cff2f5f0SNobuhiro Iwamatsu 82cff2f5f0SNobuhiro Iwamatsu #define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */ 83cff2f5f0SNobuhiro Iwamatsu 847ffc8dfbSNobuhiro Iwamatsu /* USB */ 857ffc8dfbSNobuhiro Iwamatsu #define CONFIG_USB_STORAGE 867ffc8dfbSNobuhiro Iwamatsu #define CONFIG_USB_EHCI 877ffc8dfbSNobuhiro Iwamatsu #define CONFIG_USB_EHCI_RMOBILE 887ffc8dfbSNobuhiro Iwamatsu #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 897ffc8dfbSNobuhiro Iwamatsu 902b8c0814SNobuhiro Iwamatsu /* MMCIF */ 912b8c0814SNobuhiro Iwamatsu #define CONFIG_MMC 922b8c0814SNobuhiro Iwamatsu #define CONFIG_GENERIC_MMC 932b8c0814SNobuhiro Iwamatsu 942b8c0814SNobuhiro Iwamatsu #define CONFIG_SH_MMCIF 952b8c0814SNobuhiro Iwamatsu #define CONFIG_SH_MMCIF_ADDR 0xee200000 962b8c0814SNobuhiro Iwamatsu #define CONFIG_SH_MMCIF_CLK 48000000 972b8c0814SNobuhiro Iwamatsu 988e2e5886SNobuhiro Iwamatsu /* Module stop status bits */ 998e2e5886SNobuhiro Iwamatsu /* INTC-RT */ 1008e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP0_ENA 0x00400000 1018e2e5886SNobuhiro Iwamatsu /* MSIF */ 1028e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP2_ENA 0x00002000 1038e2e5886SNobuhiro Iwamatsu /* INTC-SYS, IRQC */ 1048e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP4_ENA 0x00000180 1058e2e5886SNobuhiro Iwamatsu /* SCIF2 */ 1068e2e5886SNobuhiro Iwamatsu #define CONFIG_SMSTP7_ENA 0x00080000 1078e2e5886SNobuhiro Iwamatsu 10825f9613fSNobuhiro Iwamatsu /* SDHI */ 10925f9613fSNobuhiro Iwamatsu #define CONFIG_SH_SDHI_FREQ 97500000 11025f9613fSNobuhiro Iwamatsu 111cff2f5f0SNobuhiro Iwamatsu #endif /* __ALT_H */ 112