1 /* 2 * Copyright (C) 2011 Andes Technology Corporation 3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com> 4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #ifndef __CONFIG_H 10 #define __CONFIG_H 11 12 #include <asm/arch-ag101/ag101.h> 13 14 /* 15 * CPU and Board Configuration Options 16 */ 17 #define CONFIG_ADP_AG101P 18 19 #define CONFIG_USE_INTERRUPT 20 21 #define CONFIG_SKIP_LOWLEVEL_INIT 22 23 #define CONFIG_CMDLINE_EDITING 24 25 #define CONFIG_SYS_ICACHE_OFF 26 #define CONFIG_SYS_DCACHE_OFF 27 28 #define CONFIG_BOOTP_SEND_HOSTNAME 29 #define CONFIG_BOOTP_SERVERIP 30 31 #ifndef CONFIG_SKIP_LOWLEVEL_INIT 32 #define CONFIG_MEM_REMAP 33 #endif 34 35 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 36 #define CONFIG_SYS_TEXT_BASE 0x00500000 37 #ifdef CONFIG_OF_CONTROL 38 #undef CONFIG_OF_SEPARATE 39 #define CONFIG_OF_EMBED 40 #endif 41 #else 42 #ifdef CONFIG_MEM_REMAP 43 #define CONFIG_SYS_TEXT_BASE 0x80000000 44 #else 45 #define CONFIG_SYS_TEXT_BASE 0x00000000 46 #endif 47 #endif 48 49 /* 50 * Timer 51 */ 52 #define CONFIG_SYS_CLK_FREQ 39062500 53 #define VERSION_CLOCK CONFIG_SYS_CLK_FREQ 54 55 /* 56 * Use Externel CLOCK or PCLK 57 */ 58 #undef CONFIG_FTRTC010_EXTCLK 59 60 #ifndef CONFIG_FTRTC010_EXTCLK 61 #define CONFIG_FTRTC010_PCLK 62 #endif 63 64 #ifdef CONFIG_FTRTC010_EXTCLK 65 #define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */ 66 #else 67 #define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */ 68 #endif 69 70 #define TIMER_LOAD_VAL 0xffffffff 71 72 /* 73 * Real Time Clock 74 */ 75 #define CONFIG_RTC_FTRTC010 76 77 /* 78 * Real Time Clock Divider 79 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ) 80 */ 81 #define OSC_5MHZ (5*1000000) 82 #define OSC_CLK (4*OSC_5MHZ) 83 #define RTC_DIV_COUNT (0.5) /* Why?? */ 84 85 /* 86 * Serial console configuration 87 */ 88 89 /* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */ 90 #define CONFIG_CONS_INDEX 1 91 #define CONFIG_SYS_NS16550_SERIAL 92 #define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE 93 #ifndef CONFIG_DM_SERIAL 94 #define CONFIG_SYS_NS16550_REG_SIZE -4 95 #endif 96 #define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */ 97 98 /* 99 * Ethernet 100 */ 101 #define CONFIG_FTMAC100 102 103 /* 104 * SD (MMC) controller 105 */ 106 #define CONFIG_FTSDC010 107 #define CONFIG_FTSDC010_NUMBER 1 108 #define CONFIG_FTSDC010_SDIO 109 110 /* 111 * Miscellaneous configurable options 112 */ 113 #define CONFIG_SYS_LONGHELP /* undef to save memory */ 114 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 115 116 /* Print Buffer Size */ 117 #define CONFIG_SYS_PBSIZE \ 118 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 119 120 /* max number of command args */ 121 #define CONFIG_SYS_MAXARGS 16 122 123 /* Boot Argument Buffer Size */ 124 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE 125 126 /* 127 * Size of malloc() pool 128 */ 129 /* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */ 130 #define CONFIG_SYS_MALLOC_LEN (512 << 10) 131 132 /* 133 * AHB Controller configuration 134 */ 135 #define CONFIG_FTAHBC020S 136 137 #ifdef CONFIG_FTAHBC020S 138 #include <faraday/ftahbc020s.h> 139 140 /* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */ 141 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100 142 143 /* 144 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S, 145 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote 146 * in C language. 147 */ 148 #define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \ 149 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \ 150 FTAHBC020S_SLAVE_BSR_SIZE(0xb)) 151 #endif 152 153 /* 154 * Watchdog 155 */ 156 #define CONFIG_FTWDT010_WATCHDOG 157 158 /* 159 * PMU Power controller configuration 160 */ 161 #define CONFIG_PMU 162 #define CONFIG_FTPMU010_POWER 163 164 #ifdef CONFIG_FTPMU010_POWER 165 #include <faraday/ftpmu010.h> 166 #define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E 167 #define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \ 168 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \ 169 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \ 170 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \ 171 FTPMU010_SDRAMHTC_CKE_DCSR | \ 172 FTPMU010_SDRAMHTC_DQM_DCSR | \ 173 FTPMU010_SDRAMHTC_SDCLK_DCSR) 174 #endif 175 176 /* 177 * SDRAM controller configuration 178 */ 179 #define CONFIG_FTSDMC021 180 181 #ifdef CONFIG_FTSDMC021 182 #include <faraday/ftsdmc021.h> 183 184 #define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \ 185 FTSDMC021_TP1_TRP(1) | \ 186 FTSDMC021_TP1_TRCD(1) | \ 187 FTSDMC021_TP1_TRF(3) | \ 188 FTSDMC021_TP1_TWR(1) | \ 189 FTSDMC021_TP1_TCL(2)) 190 191 #define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \ 192 FTSDMC021_TP2_INI_REFT(8) | \ 193 FTSDMC021_TP2_REF_INTV(0x180)) 194 195 /* 196 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S, 197 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in 198 * C language. 199 */ 200 #define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \ 201 FTSDMC021_CR1_DSZ(3) | \ 202 FTSDMC021_CR1_MBW(2) | \ 203 FTSDMC021_CR1_BNKSIZE(6)) 204 205 #define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \ 206 FTSDMC021_CR2_IREF | \ 207 FTSDMC021_CR2_ISMR) 208 209 #define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 210 #define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \ 211 CONFIG_SYS_FTSDMC021_BANK0_BASE) 212 213 #define CONFIG_SYS_FTSDMC021_BANK1_BASE \ 214 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20)) 215 #define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \ 216 CONFIG_SYS_FTSDMC021_BANK1_BASE) 217 #endif 218 219 /* 220 * Physical Memory Map 221 */ 222 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 223 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 224 #else 225 #ifdef CONFIG_MEM_REMAP 226 #define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */ 227 #else 228 #define PHYS_SDRAM_0 0x80000000 /* SDRAM Bank #1 */ 229 #endif 230 #endif 231 232 #define PHYS_SDRAM_1 \ 233 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */ 234 235 #define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */ 236 237 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 238 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 239 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 240 #else 241 #ifdef CONFIG_MEM_REMAP 242 #define PHYS_SDRAM_0_SIZE 0x20000000 /* 512 MB */ 243 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */ 244 #else 245 #define PHYS_SDRAM_0_SIZE 0x08000000 /* 128 MB */ 246 #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ 247 #endif 248 #endif 249 250 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0 251 252 #ifdef CONFIG_MEM_REMAP 253 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \ 254 GENERATED_GBL_DATA_SIZE) 255 #else 256 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ 257 GENERATED_GBL_DATA_SIZE) 258 #endif /* CONFIG_MEM_REMAP */ 259 260 /* 261 * Load address and memory test area should agree with 262 * arch/nds32/config.mk. Be careful not to overwrite U-Boot itself. 263 */ 264 #define CONFIG_SYS_LOAD_ADDR 0x300000 265 266 /* memtest works on 63 MB in DRAM */ 267 #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0 268 #define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000) 269 270 /* 271 * Static memory controller configuration 272 */ 273 #define CONFIG_FTSMC020 274 275 #ifdef CONFIG_FTSMC020 276 #include <faraday/ftsmc020.h> 277 278 #define CONFIG_SYS_FTSMC020_CONFIGS { \ 279 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \ 280 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \ 281 } 282 283 #ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */ 284 #define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \ 285 FTSMC020_BANK_SIZE_32M | \ 286 FTSMC020_BANK_MBW_32) 287 288 #define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \ 289 FTSMC020_TPR_AST(1) | \ 290 FTSMC020_TPR_CTW(1) | \ 291 FTSMC020_TPR_ATI(1) | \ 292 FTSMC020_TPR_AT2(1) | \ 293 FTSMC020_TPR_WTC(1) | \ 294 FTSMC020_TPR_AHT(1) | \ 295 FTSMC020_TPR_TRNA(1)) 296 #endif 297 298 /* 299 * FLASH on ADP_AG101P is connected to BANK0 300 * Just disalbe the other BANK to avoid detection error. 301 */ 302 #define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \ 303 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \ 304 FTSMC020_BANK_SIZE_32M | \ 305 FTSMC020_BANK_MBW_32) 306 307 #define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \ 308 FTSMC020_TPR_CTW(3) | \ 309 FTSMC020_TPR_ATI(0xf) | \ 310 FTSMC020_TPR_AT2(3) | \ 311 FTSMC020_TPR_WTC(3) | \ 312 FTSMC020_TPR_AHT(3) | \ 313 FTSMC020_TPR_TRNA(0xf)) 314 315 #define FTSMC020_BANK1_CONFIG (0x00) 316 #define FTSMC020_BANK1_TIMING (0x00) 317 #endif /* CONFIG_FTSMC020 */ 318 319 /* 320 * FLASH and environment organization 321 */ 322 /* use CFI framework */ 323 #define CONFIG_SYS_FLASH_CFI 324 #define CONFIG_FLASH_CFI_DRIVER 325 326 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 327 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 328 #define CONFIG_SYS_CFI_FLASH_STATUS_POLL 329 330 /* support JEDEC */ 331 332 /* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */ 333 #ifdef CONFIG_SKIP_LOWLEVEL_INIT 334 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 335 #else 336 #ifdef CONFIG_MEM_REMAP 337 #define PHYS_FLASH_1 0x80000000 /* BANK 0 */ 338 #else 339 #define PHYS_FLASH_1 0x00000000 /* BANK 0 */ 340 #endif 341 #endif /* CONFIG_MEM_REMAP */ 342 343 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 344 #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, } 345 #define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1 346 347 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */ 348 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */ 349 350 /* max number of memory banks */ 351 /* 352 * There are 4 banks supported for this Controller, 353 * but we have only 1 bank connected to flash on board 354 */ 355 #ifndef CONFIG_SYS_MAX_FLASH_BANKS_DETECT 356 #define CONFIG_SYS_MAX_FLASH_BANKS 1 357 #endif 358 #define CONFIG_SYS_FLASH_BANKS_SIZES {0x4000000} 359 360 /* max number of sectors on one chip */ 361 #define CONFIG_FLASH_SECTOR_SIZE (0x10000*2) 362 #define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE 363 #define CONFIG_SYS_MAX_FLASH_SECT 512 364 365 /* environments */ 366 #define CONFIG_ENV_IS_IN_FLASH 367 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000) 368 #define CONFIG_ENV_SIZE 8192 369 #define CONFIG_ENV_OVERWRITE 370 371 /* 372 * For booting Linux, the board info and command line data 373 * have to be in the first 16 MB of memory, since this is 374 * the maximum mapped by the Linux kernel during initialization. 375 */ 376 377 /* Initial Memory map for Linux*/ 378 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) 379 /* Increase max gunzip size */ 380 #define CONFIG_SYS_BOOTM_LEN (64 << 20) 381 382 #endif /* __CONFIG_H */ 383